参数资料
| 型号： | A14100A-1PG257C |
| 厂商： | Microsemi SoC |
| 文件页数： | 4/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 10K GATES 257-CPGA |
| 标准包装： | 10 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 1377 |
| 输入/输出数： | 228 |
| 门数： | 10000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 通孔 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 257-BCPGA |
| 供应商设备封装： | 257-CPGA（50x50） |
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Detailed Specifications
2- 4
R e v ision 3
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into
the array. This allows the output register to be used in high-speed state machine applications. Side I/O
modules have a dedicated output segment for Y extending into the routing channels above and below
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained
in detail in the routing section).
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN
(global input enable), and SLEW (individual slew selection). See Figure 2-5.
Special I/Os
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change
once the device has been programmed. The permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is
determined by the I/O macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks
and two general purpose routed networks. The high-performance networks function up to 200 MHz,
while the general purpose routed networks function up to 150 MHz.
Figure 2-5
Function Diagram for I/O Pad Driver
PAD
OE
SLEW
DATAOUT
DATAIN
IEN
INEN
OUTEN
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A14100A-1PG257M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 10K GATES 1377 CELLS 125MHZ 0.8UM 5V 257CPGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 10K GATES 257-CPGA MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 228 I/O 257CPGA |
| A14100A-1RQ208C | 功能描述:IC FPGA 10K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A14100A-1-RQ208C | 制造商:Microsemi SOC Products Group 功能描述:FIELD PROGRAMMABLE GATE ARRAY 10000 GATES |
| A14100A-1RQ208I | 功能描述:IC FPGA 10K GATES 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A14100A-2BG313C | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA) |
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