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| 型号： | A1448EEWLT-P |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DVR BLDC FULLBRDG MLP |
| 产品变化通告： | Pre-EOL Notice 07/Feb/2012 |
| 标准包装： | 1 |
| 应用： | DC 电机驱动器，无刷（BLDC） |
| 输出数： | 1 |
| 电流 - 输出： | ±200mA |
| 电源电压： | 1.8 V ~ 4.2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-XFDFN 裸露焊盘 |
| 供应商设备封装： | 6-MLP/DFN 裸露焊盘（1.5x2） |
| 包装： | 标准包装 |
| 产品目录页面： | 1140 (CN2011-ZH PDF) |
| 其它名称： | 620-1274-6 |
A1448
Low-Voltage, Full-Bridge Brushless DC Motor Driver with
Integrated Hall Sensor IC, PWM Speed Control, Soft-Switching,
and Reverse Battery and Short Circuit Protection
Features and Benefits
? Low-voltage operation, 1.8 to 4.2 V
? Multifunction CONTROL pin input:
? Direct input PWM for speed control
? Active braking for fast stop cycle
? Sleep function to reduce average power consumption
? Reverse voltage protection on VDD and CONTROL pins
? Output thermal shutdown protection for robust performance
? Soft switching algorithm to reduce audible switching noise
and EMI
? Hall chopper stabilization technique for precise signal
response over operating range
? Antistall feature guarantees continuous rotation and
prevents overheating
? Single-chip solution for high reliability
? Miniature MLP/DFN package with industry-leading
0.40 mm maximum overall thickness
Description
The A1448 is a full-bridge motor driver designed to drive
low-voltage, brushless DC motors. The device is designed
to allow the user to control several functions with a single
input control pin. The pin allows for direct input PWM for
speed control, is used to initiate the active braking func-
tion to reduce motor stop time, and acts as an enable pin to
engage micro-power sleep mode to reduce average power
consumption when not in use. The A1448 is designed for
use in vibration motor applications in portable devices that
require fast stop-start cycles, such as haptic applications and
vibration ring tones.
Commutation of the motor is achieved by use of a single
Hall element to detect the rotational position of an alternat-
ing-pole ring magnet. A high density CMOS semiconductor
process allows the integration of all the necessary electron-
ics. This includes the Hall element, the motor control cir-
cuitry, and the output full bridge. Low-voltage design tech-
Package:
6-contact MLP/DFN
1.5 mm × 2 mm
0.40 mm maximum overall height
(EW package)
Approximate size
niques have been employed to achieve full device function-
ality down to 1.8 V V DD . This fully integrated single chip
solution provides enhanced reliability (including reverse
battery protection and output short circuit protection) and
eliminates the need for any external support components.
The A1448 employs a soft-switching algorithm to reduce
audible switching noise and EMI interference. The micro-
power sleep mode can be initiated on the CONTROL pin,
and reduces current consumption for battery management in
Continued on the next page…
Functional Block Diagram
VDD
Reverse Battery
ESD
To All Subcircuits
CONTROL
Active Braking
Sleep Mode
Full Bridge
Q1
Q2
Amp
PWM Control
Drive
Logic
ESD
VOUT1
VOUT2
Q3
Q4
Stall Detection
Thermal Shutdown
Protection
GND
1448-DS, Rev. 4
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