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参数资料
| 型号： | A2550KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC RELAY DRVR AUTO W/REG 16TSSOP |
| 标准包装： | 1 |
| 应用： | 汽车用，继电器驱动器 |
| 输出数： | 3 |
| 电源电压： | 7 V ~ 40 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1182-6 |
A2550
Relay Driver with 5 V Regulator
for Automotive Applications
Applications Information
t POR = ? 200 ms ? C POR
t POR V REF ? V TRIP(L) (3)
=
t WD = ? 200 ms ? C WD
T J = ( P D(max) R θ JA + T A ) ≤ T J(max)
t WDR = ? 14 ms ? C WD
NPOR is pulsed for a watchdog fault. For the remaining
faults, NPOR is held low for the duration of the fault. After
the fault condition is removed, NPOR remains low during
the t POR period. The latter is set by the value of the external
capacitor fed by a current source at the CPOR pin, according
to the following formula:
(2)
? μF ?
The scaling factor is simply derived from the specifications
using the typical value of I POR :
C POR I POR
Watchdog
The watchdog monitors the microcontroller to detect if
it locks up. To do so, the watchdog checks for pulses on
the Watchdog Input pin (WDI), and if they are absent for
longer than the timeout period, t WD , the watchdog activates
NPOR, which pulses periodically. t WD is proportional to
the external capacitor fed by a current source at the CWD
pin. The voltage change is 1 V, so using the typical value of
I CWD (charging) we have:
(4)
? μF ?
The pulse width for NPOR active, t WDR , also scales propor-
tionally to the value of the external capacitor at the CWD
pin. Using the typical value of I CWD (discharging) we have:
(5)
? μF ?
See the specification tables for tolerances.
When not used, disable watchdog by tying WDI to NPOR
and tying CWD low. Table 2 shows watchdog timing for the
nominal capacitances listed.
Output Overcurrent
When the OC (overcurrent) protection is triggered in a
driver, that driver is disabled for self-protection. No other
functions are affected; NPOR and VREG5 operate nor-
mally. A disabled output driver remains shut down until the
respective INx is brought low, then high again; at which time
OUTx turns on. OUTx will switch on again the next time
INx is applied. If a short-to-battery still exists, the overcur-
rent will trip each time INx is reapplied.
Sleep
The A2550 is put to sleep by holding both EN and ENBAT
low. In sleep mode all functions are shut down, including
VREG5. If the VREG5 regulator is required at all times, dis-
able sleep mode by tying ENBAT to VBB.
Power Limits
Power dissipation, P D , is limited by thermal constraints. The
maximum allowed power dissipation, P D(max) , is found from
the formula:
(6)
The maximum junction temperature, T J(max) , and the thermal
resistance, R θ JA , are given in the specification tables.
The three main contributors to power dissipation are:
? P BIAS from the supply bias current
? P REG from the linear regulator voltage drop
? P LS from low-side driver conduction
For example, to determine if T J is in an acceptable range,
given:
Table 2. Timing Set by Capacitors
C t POR t WD
( μ F) (ms) (ms)
0.1 20 20
0.22 44 44
t WDR
(ms)
1
3
R θ JA = 55°C/W , and
T A = 125°C ; and
P BIAS = V BB × I BBQ
= 14 V × 3 mA = 42 mW , and
(7)
0.47
1
94
200
94
200
7
14
P REG = ( V BB – V REG5(min) ) × I REG5
= (14 V – 4.9 V) × 20 mA= 182 mW , and
(8)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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