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参数资料
| 型号： | A29L160SERIES |
| 英文描述： | 2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only. Boot Sector Flash Memory |
| 中文描述： | 2米x 8位/ 1米× 16位CMOS 3.0伏特只。引导扇区闪存 |
| 文件页数： | 7/45页 |
| 文件大小： | 433K |
| 代理商： | A29L160SERIES |
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A29L160 Series
PRELIMINARY (July, 2002, Version 0.0)
6
AMIC Technology, Inc.
Word/Byte Configuration
The
BYTE
pin determines whether the I/O pins I/O
15
-I/O
0
operate in the byte or word configuration. If the
BYTE
pin
is set at logic ”1”, the device is in word configuration, I/O
15
-
I/O
0
are active and controlled by
CE
and
OE
.
If the
BYTE
pin is set at logic “0”, the device is in byte
configuration, and only I/O
0
-I/O
7
are active and controlled
by
CE
and
OE
. I/O
8
-I/O
14
are tri-stated, and I/O
15
pin is
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
CE
and
OE
pins to V
IL
.
CE
is the power control and
selects the device.
OE
is the output control and gates
array data to the output pins.
WE
should remain at V
IH
all
the time during read operation. The
BYTE
pin determines
whether the device outputs array data in words and bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on
the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access
until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, l
CC1
in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
WE
and
CE
to
V
IL
, and
OE
to V
IH
. For program operations, the
BYTE
pin
determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An
erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O
7
- I/O
0
. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
CC2
in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
7
- I/O
0
. Standard read cycle timings and I
CC
read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
OE
input.
The device enters the CMOS standby mode when the
CE
&
RESET
pins are both held at VCC
±
0.3V. (Note that this
is a more restricted voltage range than V
IH
.) If
CE
and
RESET
are held at V
IH
, but not within VCC
±
0.3V, the
device will be in the standby mode, but the standby current
will be greater. The device requires the standard access
time (t
CE
) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
CC3
and
I
CC4
in the DC Characteristics tables represent the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
ACC
+30ns. The
automatic sleep mode is independent of the
CE
,
WE
and
OE
control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. I
CC4
in the DC Characteristics table represents
the automatic sleep mode current specification.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A29L160TG-120 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L160TG-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L160TG-90 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L160TM-120 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| A29L160TM-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory |
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