参数资料
型号: A3250ELTTR
厂商: Allegro Microsystems Inc
文件页数: 12/16页
文件大小: 300K
描述: IC SW HALL EFFECT UNI SOT-89
标准包装: 1,000
传感范围: 50G
类型: 单极开关
电源电压: 4.2 V ~ 24 V
电流 - 电源: 10mA
电流 - 输出(最大): 20mA
输出类型: 数字,开路集电极
特点: 稳压电压
工作温度: -40°C ~ 85°C
封装/外壳: TO-243AA
供应商设备封装: SOT-89-3
包装: 带卷 (TR)
Field-Programmable, Chopper-Stabilized,
Unipolar Hall-Effect Switches
A3250 and
A3251
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
V
PH
V+
t
V
PM
V
PL
0
Address 1
Address 2
Address n ( d 63)
Figure 5. Pulse sequence to select addresses
Falling edge of final B
OP
 address digit
V
PH
V+
t
V
PM
V
PL
0
Encode Lock Bit
Enable
Address
Blow
7 pulses
65 pulses
Figure 6. Pulse sequence to encode lock bit
Lock Bit Programming. After the desired B
OP
 calibration value
is programmed, and all of the corresponding bitfield-level fuses
are blown, the device-level fuse should be blown. To do so, the
lock bit (bitfield address 65) should be encoded as 1 and have
its fuse blown. This is done in the same manner as permanently
setting the other bitfields, as shown in figure 6.
Address Selection.  After addressing mode is enabled, the 
target bitfield address, is indicated by a series of VPM pulses,
as shown in figure 3. When provisionally trying a value, this
sequence is followed by a short V
PH
 pulse, which serves to
delimit the address and set the corresponding bitfield. When
permanently setting a bitfield, the V
PH
 pulse is continued for a
longer period of time, suffienct to not only set the bitfield to 1,
but also to blow the bitfield fuse.
Enabling Addressing Mode. The first segment of code is a 
keying sequence used to enable the bitfield addressing mode. As
shown in figure 4, this segment consists of one short V
PH
 pulse,
seven or more V
PM
 pulses, and one short V
PH
 pulse, with no
supply interruptions. This sequence is designed to prevent the
device from being programmed accidentally, such as by noise on
the supply line.
V
PH
V+
t
V
PM
V
PL
0
Minimum 7 pulses
Figure 4. Addressing mode enable pulse sequence
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