参数资料
型号: A3972SB
厂商: Allegro Microsystems Inc
文件页数: 7/11页
文件大小: 0K
描述: IC MOTOR DRIVER PWM DUAL 24-DIP
标准包装: 15
应用: 步进电机驱动器
输出数: 1
电流 - 输出: ±1.5A
电压 - 负载: 15 V ~ 50 V
电源电压: 4.5 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 通孔
封装/外壳: 24-DIP(0.300",7.62mm)
供应商设备封装: 24-DIP
包装: 管件
A3972
Word 1 Bit Assignments
Dual DMOS Full-Bridge
Microstepping PWM Motor Driver
FUNCTIONAL DESCRIPTION (continued)
For example, with a master oscillator frequency of 4 MHz, the
Bit
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Function
Word select = 1
Blank-time LSB
Blank-time MSB
Off-time LSB
Off-time bit 1
Off-time bit 2
Off-time bit 3
Off-time MSB
Fast-decay time LSB
Fast-decay time bit 1
Fast-decay time bit 2
? xed off-time will be adjustable from 1.75 μ s to 63.75 μ s in
increments of 2 μ s.
D8 – D11 Fast Decay Time. These four bits set the fast-
decay portion of ? xed off-time for the internal PWM control
circuitry. The fast-decay portion is de ? ned by:
t fd = [(1 + N) x 8/f OSC ] - 1/f OSC
where N = 0….15
For example, with an oscillator frequency of 4 MHz, the fast-
decay time will be adjustable from 1.75 μ s to 31.75 μ s in incre-
ments of 2 μ s. For t fd > t off , the device will effectively operate
in fast-decay mode.
D11 Fast-decay time MSB
D12 C0 oscillator control
D13 C1 oscillator control
D14 SR control bit 1
D15 SR control bit 2
D16 Reserved for testing
D17 Reserved for testing
D18 Idle mode
D1 – D2 Blank Time. These two bits set the blank time for
the current-sense comparator. When a source driver turns on, a
current spike occurs due to the reverse-recovery currents of the
clamp diodes and/or switching transients related to distributed
capacitance in the load. To prevent this current spike from er-
D12 – D13 Oscillator Control. A 4 MHz internal oscillator
is used for the timing functions and charge-pump clock. If more
precise control is required, an external oscillator can be input
to the OSC terminal. To accommodate a wider range of system
clocks, an internal divider is provided to generate the desired
MO frequency according to the following table:
D13 D12 OSC
0 0 4 MHz internal clock
0 1 External clock
1 0 External clock/2
1 1 External clock/4
D14 – D15 Synchronous Recti ? cation.
roneously resetting the source-enable latch, the sense comparator
is blanked. The blank timer runs after the off-time counter to
provide the programmable blanking function. The blank timer is
reset when PHASE is changed.
D15
0
0
1
D14
0
1
0
Synchronous Recti ? er
Active
Disabled
Passive
D2
D1
Time
1
1
Low side only
0
0
1
1
0
1
0
1
4/ f OSC
6/ f OSC
8/ f OSC
12/ f OSC
The different modes of operation are in the synchronous recti ? -
cation section of the functional description.
D16, D17. These bits are reserved for testing and should be
programmed to zero during normal operation.
D3 – D7 Fixed Off Time. These ? ve bits set the ? xed off-time
for the internal PWM control circuitry. Fixed off-time is de ? ned
by:
t off = [(1 + N) x 8/f OSC ] - 1/f OSC
where N = 0….31
D18 Idle Mode. The device can be placed in a low power
“idle” mode by writing a “0” to D18. The outputs will be dis-
abled, the charge pump will be turned off, and the device will
draw a lower load supply currrent. The undervoltage monitor
circuit will remain active. D18 should be programmed high for
1 ms before attempting to enable any output driver.
continued next page ...
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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