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| 型号： | A3986SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 38-TSSOP |
| 产品变化通告： | A3986SLDTR-T NRND Status 08/Feb/2012 |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器，2 相 |
| 输出数： | 2 |
| 电压 - 负载： | 12 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1166-6 |
A3986
Dual Full-Bridge MOSFET Driver
with Microstepping Translator
Functional Description
Basic Operation
The A3986 is a complete microstepping FET driver with
built-in translator for easy operation with a minimum number
of control inputs. It is designed to operate 2-phase bipolar
stepper motors in full-, half-, quarter, and sixteenth-step
modes. The current in each of the two external power full-
bridges, all N-channel MOSFETs, is independently regulated
by a fixed off-time PWM control circuit. The full-bridge
current at each step is set by the value of an external cur-
rent sense resistor, R SENSE X , in the ground connection to the
bridge, a reference voltage, V REF , and the output of the DAC
controlled by the translator.
The use of PWM with N-channel MOSFETs provides the
most cost-effective solution for a high efficiency motor
drive. The A3986 provides all the necessary circuits to
ensure that the gate-source voltage of both high-side and
low-side external MOSFETs are above 10 V, and that there is
no cross-conduction (shoot through) in the external bridge.
Specific functions are described more fully in the following
sections.
Power Supplies
Two power connections are required. The motor power sup-
ply should be connected to VBB to provide the gate drive
levels. Power for internal logic is provided by the VDD
input. Internal logic is designed to operate from 3 to 5.5 V,
allowing the use of 3.3 or 5 V external logic interface cir-
cuits.
GND The ground pin is a reference voltage for internal logic
and analog circuits. There is no large current flow through
this pin. To avoid any noise from switching circuits, this
should have an independent trace to the supply ground star
point.
VREG The voltage at this pin is generated by a low-drop-out
linear regulator from the VBB supply. It is used to oper-
ate the low-side gate drive outputs, GL xx , and to provide
the charging current for the bootstrap capacitors, CBOOT x .
To limit the voltage drop when the charge current is pro-
vided, this pin should be decoupled with a ceramic capaci-
tor, CREG, to ground. The value C REG should typically
be 40 times the value of the bootstrap capacitor for PWM
frequencies up to 14 kHz. Above 14 kHz, the minimum
recommended value can be determined from the following
formula:
C REG > C BOOT × 3 × f PWM ,
where C REG and C BOOT are in nF, and f PWM is the maximum
PWM frequency, in kHz. V REG is monitored, and if the volt-
age becomes too low, the outputs will be disabled.
REF The reference voltage, V REF , at this pin sets the
maximum (100%) peak current. The REF input is internally
limited to 2 V when a 20 k ?? pull-up resistor is connected
between VREF and VDD . This allows the maximum refer-
ence voltage to be set without the need for an externally-
generated voltage. An external reference voltage below the
maximum can also be input on this pin. The voltage at VREF
is divided by 8 to produce the DAC reference voltage level.
OSC The internal FET control timing is derived from a
master clock running at 4 MHz typical. A resistor, ROSC,
connected from the OSC pin to GND sets the frequency (in
MHz) to approximately:
f OSC ≈ 100 / (6 + 1.9 × R OSC ) ,
where R OSC , in k ? , is typically between 50 k ? and 10 k ? .
The master oscillator period is used to derive the PWM off-
time, dead time, and blanking time.
Gate Drive
The A3986 is designed to drive external power N-channel
MOSFETs. It supplies the transient currents necessary to
quickly charge and discharge the external FET gate capaci-
tance in order to reduce dissipation in the external FET
during switching. The charge and discharge rate can be
controlled using an external resistor , RGx, in series with
the connection to the gate of the FET. Cross-conduction is
prevented by the gate drive circuits which introduce a dead
time, t DEAD , between switching one FET off and the comple-
mentary FET on. t DEAD is at least 3 periods of the master
oscillator but can be up to 1 cycle longer to allow oscillator
synchronization.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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