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| 型号： | A3986SLDTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/17页 |
| 文件大小： | 0K |
| 描述： | IC DRIVER MICROSTEPPING 38-TSSOP |
| 产品变化通告： | A3986SLDTR-T NRND Status 08/Feb/2012 |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器，2 相 |
| 输出数： | 2 |
| 电压 - 负载： | 12 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1166-6 |
A3986
Dual Full-Bridge MOSFET Driver
with Microstepping Translator
of source and sink MOSFETs are enabled and current flows
through the motor winding and the current sense resistor,
RSENSE x . When the voltage across RSENSE x equals the
DAC output voltage, the current sense comparator resets
the PWM latch, which turns off the source MOSFET (slow
decay mode) or the sink and source MOSFETs (fast decay
mode). The maximum value of current limiting is set by the
selection of R SENSE and the voltage at the REF input, with a
transconductance function approximated by:
I TRIP(max) = V REF / (8 × R SENSE )
The DAC, controlled by the translator, reduces the refer-
ence voltage, V REF , in precise steps to produce the required
sinusoidal reference levels for the current sense comparator.
This limits the phase current trip level, I TRIP , to a portion of
the maximum current level, I TRIP(max) , defined by:
I TRIP = (% I TRIP(max) / 100) × I TRIP(max)
See table 3 for % I TRIP(max) at each step.
Fixed Off-Time The internal PWM current control
circuitry uses the master oscillator to control the length of
time the power MOSFETs remain off. The off-time, t OFF ,
is nominally 87 cycles of the master oscillator (21.75 μ s at
4 MHz), but may be up to 1 cycle longer to synchronize with
the master oscillator.
Blanking This function blanks the output of the current
sense comparator when the outputs are switched by the
internal current control. The comparator output is blanked to
prevent false overcurrent detection due to reverse recovery
currents of the clamp diodes and switching transients related
to the capacitance of the load. The blank time, t BLANK , is
6 cycles of the master oscillator (1.5 μ s at 4 MHz). Because
the t BLANK follows after the end of t OFF , no synchronization
error occurs.
Dead Time To prevent cross-conduction (shoot through)
in the power full-bridge, a dead time is introduced between
switching one MOSFET off and switching the complemen-
tary MOSFET on. The dead time, t DEAD , is 3 cycles of the
master oscillator (750 ns at 4MHz), but may be up to 1 cycle
longer to synchronize with the master oscillator.
ENABLE This input simply turns off all the power
MOSFETs. When set at logic high, the outputs are disabled.
When set at logic low, the internal control enables the out-
puts as required. Inputs to the translator (STEP, DIR, MS1,
and MS2) and the internal sequencing logic are all active
independent of the ENABLE input state.
RESET An active-low control input used to minimize
power consumption when not in use. This disables much of
the internal circuitry, including the output MOSFETs and
internal regulator. When set at logic high, allows normal
operation and start-up of the device in the home position.
When coming out of sleep mode, wait 1 ms before issuing a
STEP command, to allow the internal regulator to stabilize.
The outputs can also be reset to the home position without
entering sleep mode. To do so, pulse the RESET input low,
with a pulse width between t wR(min) and t wR(max) .
Mixed Decay Operation
Mixed decay is a technique that provides greater control
of phase currents while the current is decreasing. When a
stepper motor is driven at high speed, the back EMF from
the motor will lag behind the driving current. If a passive
current decay mode, such as slow decay, is used in the cur-
rent control scheme, then the motor back EMF can cause the
phase current to rise out of control. Mixed decay eliminates
this effect by putting the full-bridge initially into fast decay,
and then switching to slow decay after some time. Because
fast decay is an active (driven) decay mode, this portion of
the current decay cycle will ensure that the current remains
in control. Using fast decay for the full current decay time
(off-time) would result in a large ripple current, but switch-
ing to slow decay once the current is in control will reduce
the ripple current value. The portion of the off-time that the
full-bridge has to remain in fast decay will depend on the
characteristics and the speed of the motor.
When the phase current is rising, the motor back EMF will
not affect the current control and slow decay may be used to
minimize the phase current ripple. The A3986 automatically
switches between slow decay, when the current is rising, and
mixed decay, when the current is falling. The portion of the
off-time that the full-bridge remains in fast decay is defined
by the PFD1 and PFD2 inputs.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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