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参数资料
| 型号： | A3P030-FQN48 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 768 CLBS, 30000 GATES, 350 MHz, QCC48 |
| 封装： | 8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, QFN-48 |
| 文件页数： | 47/49页 |
| 文件大小： | 5893K |
| 代理商： | A3P030-FQN48 |
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ProASIC3 DC and Switching Characteristics
2- 80
v1.3
Table 2-100 A3P060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49
ns
tRCKH
Input HIGH Delay for Global Clock
0.700.96 0.801.090.941.281.131.54
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-101 A3P125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
–F
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input LOW Delay for Global Clock
0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58
ns
tRCKH
Input HIGH Delay for Global Clock
0.761.02 0.871.161.021.371.231.64
ns
tRCKMPWH Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
0.41
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
相关PDF资料 |
PDF描述 |
|---|---|
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| A3P030-QN132II | FPGA, 768 CLBS, 30000 GATES, 350 MHz, BCC132 |
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相关代理商/技术参数 |
参数描述 |
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| A3P030-FQNG132 | 制造商:Microsemi Corporation 功能描述:FPGA PROASIC3 30K GATES 193MHZ 130NM 1.5V 132QFN - Trays |
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| A3P030-FVQ144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
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