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参数资料
型号： A3PN060-2VQ100I
厂商： Microsemi SoC
文件页数： 12/114页
文件大小： 0K
描述： IC FPGA NANO 60K GATES 100-VQFP
标准包装： 90
系列： ProASIC3 nano
RAM 位总计： 18432
输入/输出数： 71
门数： 60000
电源电压： 1.425 V ~ 1.575 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 100-TQFP
供应商设备封装： 100-VQFP（14x14）
ProASIC3 nano Flash FPGAs
Revision 11
5-3
Revision 8
(continued)
The following tables were updated with available information:
Table 2-8 Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software
Settings; Table 2-9 Summary of I/O Output Buffer Power (per pin) – Default I/O
Software Settings1; Table 2-10 Different Components Contributing to Dynamic
Power Consumption in ProASIC3 nano Devices; Table 2-14 Summary of Maximum
and Minimum DC Input and Output Levels; Table 2-18 Summary of I/O Timing
Characteristics—Software Default Settings (at 35 pF); Table 2-19 Summary of I/O
Timing Characteristics—Software Default Settings (at 10 pF)
2-6
through
2-18
Table 2-22 I/O Weak Pull-Up/Pull-Down Resistances was revised to add wide range
data and correct the formulas in the table notes (SAR 21348).
2-19
The text introducing Table 2-24 Duration of Short Circuit Event before Failure was
revised to state six months at 100° instead of three months at 110° for reliability
concerns. The row for 110° was removed from the table.
2-20
Table 2-26 I/O Input Rise Time, Fall Time, and Related I/O Reliability was revised to
give values with Schmitt trigger disabled and enabled (SAR 24634). The temperature
for reliability was changed to 100C.
2-21
Table 2-33 Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS
Wide Range and the timing tables in the "Single-Ended I/O Characteristics" section
were updated with available information. The timing tables for 3.3 V LVCMOS wide
range are new.
2-22
The following sentence was deleted from the "2.5 V LVCMOS" section: "It uses a 5 V–
tolerant input buffer and push-pull output buffer."
2-30
Values for tDDRISUD and FDDRIMAX were updated in Table 2-62 Input DDR
Propagation Delays. Values for FDDOMAX were added to Table 2-64 Output DDR
Propagation Delays (SAR 23919).
2-46,
2-48
Table 2-67 A3PN010 Global Resource through Table 2-70 A3PN060 Global
Resource were updated with available information.
2-54
through
2-55
Table 2-73 ProASIC3 nano CCC/PLL Specification was revised (SAR 79390).
2-57
Revision
Changes
Page
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相关代理商/技术参数
参数描述
A3PN060-2VQG100 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN060-2VQG100I 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN060-DIELOT 制造商:Microsemi Corporation 功能描述:A3PN060-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
A3PN060-VQ100 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN060-VQ100I 功能描述:IC FPGA NANO 60K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
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