参数资料
型号: A3PN125-1VQG100
元件分类: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封装: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件页数: 22/106页
文件大小: 3324K
代理商: A3PN125-1VQG100
ProASIC3 nano DC and Switching Characteristics
2- 8
R e v ision 8
Power Consumption of Various Internal Resources
Table 2-10 Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices
Parameter
Definition
Device Specific Dynamic Contributions
(W/MHz)
A3PN2
5
0
A3PN1
2
5
A3PN0
6
0
A3PN0
2
0
A3PN0
1
5
A3PN0
1
0
PAC1
Clock contribution of a Global Rib
11.03
9.3
PAC2
Clock contribution of a Global Spine
1.58
0.81
0.4
PAC3
Clock contribution of a VersaTile row
0.81
PAC4
Clock contribution of a VersaTile used as a
sequential module
0.12
PAC5
First contribution of a VersaTile used as a
sequential module
0.07
PAC6
Second contribution of a VersaTile used as a
sequential module
0.29
PAC7
Contribution of a VersaTile used as a
combinatorial Module
0.29
PAC8
Average contribution of a routing net
0.70
PAC9
Contribution of an I/O input pin
(standard-dependent)
PAC10
Contribution of an I/O output pin
(standard-dependent)
PAC11
Average contribution of a RAM block during a read
operation
25.00
N/A
PAC12
Average contribution of a RAM block during a write
operation
30.00
N/A
PAC13
Dynamic contribution for PLL
2.60
N/A
Note:
For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet
calculator or SmartPower tool in Libero Integrated Design Environment (IDE) software.
Table 2-11 Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices
Parameter
Definition
Device Specific Static Power (mW)
A3PN25
0
A3PN12
5
A3PN06
0
A3PN02
0
A3PN01
5
A3PN01
0
PDC1
Array static power in Active mode
PDC4
Static PLL contribution 1
2.55
N/A
PDC5
Bank quiescent power (VCCI-dependent)
Notes:
1. Minimum contribution of the PLL when running at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel Power spreadsheet calculator
or SmartPower tool in Libero IDE.
相关PDF资料
PDF描述
A3PN125-2VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-2VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
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A3PN125-2VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA,CSBGA 供应商设备封装:289-CSP(14x14)
A3PN125-2VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA,CSBGA 供应商设备封装:289-CSP(14x14)
A3PN125-2VQG100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA,CSBGA 供应商设备封装:289-CSP(14x14)
A3PN125-2VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA(现场可编程门阵列) 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA,CSBGA 供应商设备封装:289-CSP(14x14)