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参数资料
型号： A3PN125-VQ100
元件分类： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, PQFP100
封装： 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100
文件页数： 4/106页
文件大小： 3324K
代理商： A3PN125-VQ100
R e visio n 8
4 -1
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the ProASIC3 nano
datasheet.
Revision
Changes
Page
Revision 8
(April 2010)
References to differential inputs were removed from the datasheet, since
ProASIC3 nano devices do not support differential inputs (SAR 21449).
N/A
The "ProASIC3 nano Device Status" table is new.
II
The JTAG DC voltage was revised in Table 2-2 Recommended Operating
Conditions 1, 2 (SAR 24052). The maximum value for VPUMP programming
voltage (operation mode) was changed from 3.45 V to 3.6 V (SAR 25220).
2-2
The highest temperature in Table 2-6 Temperature and Voltage Derating Factors
for Timing Delays was changed to 100C.
2-5
The typical value for A3PN010 was revised in Table 2-7 Quiescent Supply
Current Characteristics. The note was revised to remove the statement that
values do not include I/O static contribution.
2-6
The following tables were updated with available information:
Table 2-8 Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software
Settings
Table 2-9 Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings1
Table 2-10 Different Components Contributing to Dynamic Power Consumption
in ProASIC3 nano Devices
Table 2-14 Summary of Maximum and Minimum DC Input and Output Levels
Table 2-18 Summary of I/O Timing Characteristics—Software Default Settings
(at 35 pF)
Table 2-19 Summary of I/O Timing Characteristics—Software Default Settings
(at 10 pF)
2-6
through
2-18
Table 2-22 I/O Weak Pull-Up/Pull-Down Resistances was revised to add wide
range data and correct the formulas in the table notes (SAR 21348).
2-19
The text introducing Table 2-24 Duration of Short Circuit Event before Failure
was revised to state six months at 100° instead of three months at 110° for
reliability concerns. The row for 110° was removed from the table.
2-20
Table 2-26 I/O Input Rise Time, Fall Time, and Related I/O Reliability was
revised to give values with Schmitt trigger disabled and enabled (SAR 24634).
The temperature for reliability was changed to 100C.
2-21
Table 2-33 Minimum and Maximum DC Input and Output Levels for 3.3 V
LVCMOS Wide Range and the timing tables in the "Single-Ended I/O
Characteristics" section were updated with available information. The timing
tables for 3.3 V LVCMOS wide range are new.
2-22
The following sentence was deleted from the "2.5 V LVCMOS" section: "It uses a
5 V–tolerant input buffer and push-pull output buffer."
2-30
相关PDF资料
PDF描述
A3PN125-VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-Z1VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-Z1VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-Z1VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
相关代理商/技术参数
参数描述
A3PN125-VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN125-VQG100 功能描述:IC FPGA NANO 1024MAC 100VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:60 系列:XP LAB/CLB数:- 逻辑元件/单元数:10000 RAM 位总计:221184 输入/输出数:244 门数:- 电源电压:1.71 V ~ 3.465 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:388-BBGA 供应商设备封装:388-FPBGA（23x23） 其它名称:220-1241
A3PN125-VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN125-Z1VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A3PN125-Z1VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
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