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| 型号： | A3PN125-VQ100I |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
| 封装： | 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100 |
| 文件页数： | 11/106页 |
| 文件大小： | 3324K |
| 代理商： | A3PN125-VQ100I |
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ProASIC3 nano Device Overview
1- 6
R e v ision 8
The Actel ProASIC3 nano development software solutions, Libero Integrated Design Environment (IDE)
and Designer, have extensive support for the FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring a unique serial number in each part. Another
feature enables the inclusion of static data for system version control. Data for the FlashROM can be
generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive
programming file support is also included to allow for easy programming of large numbers of parts with
differing FlashROM contents.
SRAM and FIFO
ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along
their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available
memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have
independent read and write ports that can be configured with different bit widths on each port. For
example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM
blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro
(except in A3PN030 and smaller devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures
provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and
A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices
use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any
PLLs or programmable delays.
For devices using the six CCC block architecture, these six CCC blocks are located at the four corners
and the centers of the east and west sides.
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the
FPGA core or from dedicated connections to the CCC block, which are located near the CCC.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time = 300 s (for PLL only)
Low power consumption of 5 mW
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC) (for PLL only)
相关PDF资料 |
PDF描述 |
|---|---|
| A3PN125-VQ100 | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
| A3PN125-VQG100I | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
| A3PN125-VQG100 | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
| A3PN125-Z1VQ100I | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
| A3PN125-Z1VQ100 | FPGA, 3072 CLBS, 125000 GATES, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A3PN125-VQG100 | 功能描述:IC FPGA NANO 1024MAC 100VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:60 系列:XP LAB/CLB数:- 逻辑元件/单元数:10000 RAM 位总计:221184 输入/输出数:244 门数:- 电源电压:1.71 V ~ 3.465 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:388-BBGA 供应商设备封装:388-FPBGA（23x23） 其它名称:220-1241 |
| A3PN125-VQG100I | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN125-Z1VQ100 | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN125-Z1VQ100I | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
| A3PN125-Z1VQG100 | 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3 nano 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14） |
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