参数资料
型号: A40MX04-PQ100AX79
元件分类: FPGA
英文描述: FPGA, 547 CLBS, 6000 GATES, 116 MHz, PQFP100
封装: PLASTIC, QFP-100
文件页数: 61/124页
文件大小: 3142K
代理商: A40MX04-PQ100AX79
40MX and 42MX FPGA Families
v6.1
1-35
PCI System Timing Specification
Table 26 and Table 27 list the critical PCI timing
parameters and the corresponding timing parameters
for the MX PCI-compliant devices.
PCI Models
Actel provides synthesizable VHDL and Verilog-HDL
models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Actel sales
representative for more details.
Table 26
Clock Specification for 33 MHz PCI
Symbol
Parameter
PCI
A42MX24
A42MX36
Units
Min.
Max.
Min.
Max.
Min.
Max.
tCYC
CLK Cycle Time
30
4.0
4.0
ns
tHIGH
CLK High Time
11
1.9
1.9
ns
tLOW
CLK Low Time
11
–1.9
ns
Table 27
Timing Parameters for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
Parameter
Min.Max.Min.Max.Min.Max.
Units
tVAL
CLK to Signal Valid—Bused Signals
2
11
2.0
9.0
2.0
9.0
ns
tVAL(PTP)
CLK to Signal Valid—Point-to-Point
2 2
12
2.0
9.0
2.0
9.0
ns
tON
Float to Active
2
2.0
4.0
2.0
4.0
ns
tOFF
Active to Float
28
8.31
–8.31
ns
tSU
Input Set-Up Time to CLK—Bused Signals
7
1.5
1.5
ns
tSU(PTP)
Input Set-Up Time to CLK—Point-to-Point
10, 12 2
–1.5
1.5
ns
tH
Input Hold to CLK
0
0
0
ns
Notes:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed signals.
GNT# has a setup of 10; REW# has a setup of 12.
相关PDF资料
PDF描述
A40MX04-PQ100A FPGA, 547 CLBS, 6000 GATES, 116 MHz, PQFP100
A40MX04-PQ100IX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100I FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100MX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
相关代理商/技术参数
参数描述
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A40MX04-PQ208A 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families
A40MX04PQG100 制造商:Microsemi SOC Products Group 功能描述: