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| 型号： | A40MX04-PQ100IX79 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 2/124页 |
| 文件大小： | 3142K |
| 代理商： | A40MX04-PQ100IX79 |
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40MX and 42MX FPGA Families
1- 4
v6.1
Routing Structure
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
continuous or split into segments. Varying segment
lengths allow the interconnect of over 90% of design
tracks to occur with only two antifuse connections.
Segments can be joined together at the ends using
antifuses to increase their lengths up to the full length of
the track. All interconnects can be accomplished with a
maximum of four antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or
are divided into multiple segments and are located in
between the rows of modules. Any segment that spans
more than one-third of the row length is considered a
long horizontal segment. A typical channel is shown in
Figure 1-6. Within horizontal routing, dedicated routing
tracks are used for global clock networks and for power
and ground tie-off tracks. Non-dedicated tracks are used
for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long. Long tracks span the column length of
the module, and can be divided into multiple segments.
Each segment in an input track is dedicated to the input
of a particular module; each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two
above and two below), except near the top and bottom
of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in
Antifuse Structures
An antifuse is a "normally open" structure. The use of
antifuses to implement a programmable logic device
results in highly testable structures as well as efficient
programming algorithms. There are no pre-existing
connections; temporary connections can be made using
pass transistors. These temporary connections can isolate
individual antifuses to be programmed and individual
circuit structures to be tested, which can be done before
and after programming. For instance, all metal tracks can
be tested for continuity and shorts between adjacent
tracks, and the functionality of all logic modules can be
verified.
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following (Figure 1-7 on page 1-5):
Externally from the CLKA pad, using CLKBUF
buffer
Externally from the CLKB pad, using CLKBUF
buffer
Internally from the CLKINTA input, using CLKINT
buffer
Internally from the CLKINTB input, using CLKINT
buffer
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure 1-8 on
page 1-5). Each quadrant clock provides a local, high-
fanout resource to the contiguous logic modules within
its quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
Figure 1-6 MX Routing Structure
Segmented
Horizontal
Routing
Logic
Modules
Antifuses
Vertical Routing Tracks
相关PDF资料 |
PDF描述 |
|---|---|
| A40MX04-PQ100I | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100 |
| A40MX04-PQ100MX79 | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100 |
| A40MX04-PQ100M | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100 |
| A40MX04-PQ100X79 | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100 |
| A40MX04-PQ100 | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A40MX04-PQ100M | 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 6K Gates 547 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 100PQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:83MHZ/139MHZ 0.45UM TECHNOLOGY 3.3V/5V 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP |
| A40MX04-PQ208A | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families |
| A40MX04PQG100 | 制造商:Microsemi SOC Products Group 功能描述: |
| A40MX04-PQG100 | 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17） |
| A40MX04-PQG100A | 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17） |
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