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参数资料
型号： A40MX04-PQ100IX79
元件分类： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
封装： PLASTIC, QFP-100
文件页数： 97/124页
文件大小： 3142K
代理商： A40MX04-PQ100IX79
40MX and 42MX FPGA Families
1- 68
v6.1
TTL Output Module Timing5 (Continued)
tLH
I/O Latch Output Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
15.9
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
Capacitive Loading, LOW to HIGH
0.05
0.06
0.07
0.10
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.05
0.06
0.08
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
4.8
5.3
5.5
6.4
9.0
ns
tDHL
Data-to-Pad LOW
3.5
3.9
4.1
4.9
6.8
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.4
4.0
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.0
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
6.8
7.6
8.6
10.1
14.2
ns
tGHL
G-to-Pad LOW
6.8
7.6
8.6
10.1
14.2
ns
tLSU
I/O Latch Set-Up
0.7
0.8
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.7
8.5
9.6
11.3
15.9
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
14.8
16.5
18.7
22.0
30.8
ns
dTLH
Capacitive Loading, LOW to HIGH
0.05
0.06
0.07
0.10
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.04
0.05
0.06
0.08
ns/pF
tHEXT
Input Latch External
Hold
FO=32
FO=486
3.9
4.6
4.3
5.2
4.9
5.8
5.7
6.9
8.1
9.6
ns
tP
Minimum Period
(1/fMAX)
FO=32
FO=486
7.8
8.6
8.7
9.5
10.4
10.8
11.9
18.2
19.9
ns
Table 37
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相关PDF资料
PDF描述
A40MX04-PQ100I FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100MX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100X79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
相关代理商/技术参数
参数描述
A40MX04-PQ100M 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 6K Gates 547 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 100PQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:83MHZ/139MHZ 0.45UM TECHNOLOGY 3.3V/5V 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP
A40MX04-PQ208A 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families
A40MX04PQG100 制造商:Microsemi SOC Products Group 功能描述:
A40MX04-PQG100 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
A40MX04-PQG100A 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
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