收藏本站
参数资料
型号： A42MX16-1PQ100
厂商： Microsemi SoC
文件页数： 101/142页
文件大小： 0K
描述： IC FPGA MX SGL CHIP 24K 100-PQFP
标准包装： 66
系列： MX
输入/输出数： 83
门数： 24000
电源电压： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安装类型： 表面贴装
工作温度： 0°C ~ 70°C
封装/外壳： 100-BQFP
供应商设备封装： 100-PQFP（14x20）
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 57
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.8
2.17
3.0
ns
tINYL
Pad-to-Y LOW
1.2
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
1.8
2.0
2.3
2.7
3.7
ns
tINGL
G to Y LOW
1.8
2.0
2.3
2.7
3.7
ns
Input Module Predicted Routing Delays2
tIRD1
FO = 1 Routing Delay
2.8
3.2
3.6
4.2
5.9
ns
tIRD2
FO = 2 Routing Delay
3.2
3.5
4.0
4.7
6.6
ns
tIRD3
FO = 3 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD4
FO = 4 Routing Delay
3.9
4.3
4.9
5.7
8.0
ns
tIRD8
FO = 8 Routing Delay
5.2
5.8
6.6
7.7
10.8
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 256
4.1
4.5
5.0
5.1
5.6
6.0
6.7
8.4
9.3
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 256
5.0
5.4
5.5
6.0
6.2
6.8
7.3
8.0
10.2
11.2
ns
tPWH
Minimum Pulse Width
HIGH
FO = 32
FO = 256
1.7
1.9
2.1
2.3
2.5
2.7
3.5
3.8
ns
tPWL
Minimum Pulse Width
LOW
FO = 32
FO = 256
1.7
1.9
2.1
2.3
2.5
2.7
3.5
3.8
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
0.4
0.5
0.6
0.9
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 256
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 256
3.3
3.7
4.1
4.2
4.6
4.9
5.5
6.9
7.6
ns
tP
Minimum Period
FO = 32
FO = 256
5.6
6.1
6.2
6.8
6.7
7.4
7.8
8.5
12.9
14.2
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
177
161
146
148
135
129
117
77
70
MHz
Table 1-33 A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Units
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相关PDF资料
PDF描述
A42MX16-1PQG100 IC FPGA MX SGL CHIP 24K 100-PQFP
A42MX16-PQG100I IC FPGA MX SGL CHIP 24K 100-PQFP
RSM43DRMD CONN EDGECARD 86POS .156 WW
ABC43DRYS-S93 CONN EDGECARD 86POS DIP .100 SLD
HMM43DRXN CONN EDGECARD 86POS DIP .156 SLD
相关代理商/技术参数
参数描述
A42MX16-1PQ100A 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PQ100B 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families
A42MX16-1PQ100ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1PQ100I 功能描述:IC FPGA MX SGL CHIP 24K 100-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27）
A42MX16-1PQ100M 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 100PQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 100-PQFP
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*