参数资料
| 型号： | A42MX16-1VQG100 |
| 厂商： | Microsemi SoC |
| 文件页数： | 132/142页 |
| 文件大小： | 0K |
| 描述： | IC FPGA MX SGL CHIP 24K 100-VQFP |
| 标准包装： | 90 |
| 系列： | MX |
| 输入/输出数： | 83 |
| 门数： | 24000 |
| 电源电压： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 100-TQFP |
| 供应商设备封装： | 100-VQFP（14x14） |
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40MX and 42MX FPGA Families
Re vi s i on 11
1-5
uncommitted and can be assigned during routing. Each output segment spans four channels (two above
and two below), except near the top and bottom of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example of vertical routing tracks and segments is shown
in Figure 1-6.
Antifuse Structures
An antifuse is a "normally open" structure. The use of antifuses to implement a programmable logic
device results in highly testable structures as well as efficient programming algorithms. There are no pre-
existing connections; temporary connections can be made using pass transistors. These temporary
connections can isolate individual antifuses to be programmed and individual circuit structures to be
tested, which can be done before and after programming. For instance, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Clock Networks
The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK
network by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA
and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal
from any of the following (Figure 1-7 on page 1-6):
Externally from the CLKA pad, using CLKBUF buffer
Externally from the CLKB pad, using CLKBUF buffer
Internally from the CLKINTA input, using CLKINT buffer
Internally from the CLKINTB input, using CLKINT buffer
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control resources, called quadrant clock networks
(Figure 1-8 on page 1-6). Each quadrant clock provides a local, high-fanout resource to the contiguous
logic modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O
Figure 1-6
MX Routing Structure
Segmented
Horizontal
Routing
Logic
Modules
Antifuses
Vertical Routing Tracks
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX16-VQG100I | IC FPGA MX SGL CHIP 24K 100-VQFP |
| AYM40DRSH | CONN EDGECARD 80POS DIP .156 SLD |
| M1AFS600-2FGG256 | IC FPGA 4MB FLASH 600K 256-FBGA |
| P1AFS600-2FG256 | IC FPGA PIGEON POINT 256-FBGA |
| ASM40DRSH | CONN EDGECARD 80POS DIP .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX16-1VQG100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX16-1VQG100M | 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 100VQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100VQFP |
| A42MX16-2BG100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2BG100B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:40MX and 42MX FPGA Families |
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