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| 型号： | A42MX24-3VQ100 |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件页数： | 54/93页 |
| 文件大小： | 854K |
| 代理商： | A42MX24-3VQ100 |
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58
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
TX/RX-A (I/O)
D1, D2, E1
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation trans-
formers.
TX/RX-A (I/O)
G1, H1, H2
TX/RX-B (I/O)
U11, V11, V12
TX/RX-B (I/O)
U15, V14, V15
TABLE 58. 1553 ISOLATION TRANSFORMER
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
D1, D2, E1, E2
G1, G2, H1, H2
L1, L2, M1, M2
P1, P2, R1, R2
BU-64743B8
BU-64843B8
BU-64863B8
BALL
SNGL_END (I)
No Connect "NC" if
utilizing "Built-In"
Transceivers
If SNGL_END is connected to logic "0" the Manchester decoder inputs
will be configured to accept single-ended input signals (e.g.,MIL-STD-
1773 fiber optic receiver outputs). If SNGL_END is connected to logic
"1," the decoder inputs will be configured to accept standard double-
ended Manchester bi-phase input signals (i.e., MIL-STD-1553 receiver
outputs).
These two signals MUST be separated for "Transceiverless" operation.
Transmitter inhibit inputs for Channel A of external MIL-STD-1553
transmitters. To enable transmitter this input should be connected to
logic "0". To force a shutdown of Channel A, a value of logic "1" should
be applied to the respective TXINH input.
Digital transmit inhibit outputs. Connect to TX_INH_OUT inputs of
external MIL-STD-1553 transceiver. Asserted high to inhibit when not
transmitting on the respective bus.
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXINH_IN_A
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
TXINH_OUT_A
TXDATA_IN_A
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
TABLE 59. MANDATORY ADDITIONAL CONNECTIONS & INTERFACE TO EXTERNAL TRANSCEIVER
SIGNAL NAME
FOR USE WITH EXTERNAL TRANSCEIVERS
"TRANSCEIVERLESS"
USING INTERNAL
"BUILT-IN"
TRANSCEIVERS
A15
A4
A5
C8
D14
E7
E8
C7
TXDATA_OUT_A
B8
C8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase transmit data outputs. Connect directly to
corresponding inputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
TXDATA_IN_A
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
C4
D7
TXDATA_OUT_A
C5
D8
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_A
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
D10
G8
RXDATA_OUT_A
E10
G7
These two signals MUST be separated for "Transceiverless" operation.
Digital manchester biphase receive data inputs. Connect directly to
corresponding outputs of a MIL-STD-1553 or MIL-STD-1773 (fiber
optic) transceiver.
RXDATA_IN_A
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
E9
H8
RXDATA_OUT_A
F9
H7
These two signals MUST be separated for "Transceiverless" operation.
Transmitter inhibit inputs for Channel B of external MIL-STD-1553
transmitters. To enable transmitter this input should be connected to
logic "0". To force a shutdown of Channel B, a value of logic "1" should
be applied to the respective TXINH input.
Digital transmit inhibit outputs. Connect to TX_INH_OUT inputs of
external MIL-STD-1553 transceiver. Asserted high to inhibit when not
transmitting on the respective bus.
TXINH_IN_B
These two signals
MUST be directly
connected for normal
"Built-In" transceiver
operation.
T8
N7
TXINH_OUT_B
R8
N8
BU-64840B3
BU-64860B3
BU-64743B8
BU-64843B8
BU-64863B8
BALL
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX24-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX24-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX36-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX36-2TQ100 | 40MX and 42MX FPGA Families |
相关代理商/技术参数 |
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| A42MX24-FPL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
| A42MX24-FPQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
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