参数资料
| 型号： | A42MX36-FPQ208 |
| 厂商： | Microsemi SoC |
| 文件页数： | 52/142页 |
| 文件大小： | 0K |
| 描述： | IC FPGA MX SGL CHIP 54K 208-PQFP |
| 标准包装： | 24 |
| 系列： | MX |
| RAM 位总计： | 2560 |
| 输入/输出数： | 176 |
| 门数： | 54000 |
| 电源电压： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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40MX and 42MX FPGA Families
Re vi s i on 11
1 - 13
Design Consideration
It is recommended to use a series 70
Ω termination resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70
Ω series termination is used to prevent data transmission corruption
during probing and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint
Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms
for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP
(test access port), TAP controller, test data registers and instruction register (Figure 1-13 on page 1-14).
This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and
BYPASS) and some optional instructions. Table 1-3 on page 1-14 describes the ports that control JTAG
testing, while Table 1-4 on page 1-14 describes the test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input),
TDI and TDO (test data input and output), and TMS (test mode selector).
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be
present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the
instruction register or the data register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for
five TCK cycles.
42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification,
and boundary scan. The bypass register is selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices in a test data path. The 32-bit device
identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part
number and version). The boundary-scan register observes and controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and
parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a
device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The
Table 1-2
Device Configuration Options for Probe Capability
Security Fuse(s)
Programmed
Mode
PRA, PRB1
SDI, SDO, DCLK1
No
LOW
User I/Os2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are
active during probing, input signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin
Descriptions" section on page 1-83 for information on unused I/O pins.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-FPQG208 | IC FPGA MX SGL CHIP 54K 208-PQFP |
| EP4CGX75CF23I7 | IC CYCLONE IV GX FPGA 75K 484FBG |
| EP4CGX75CF23C6 | IC CYCLONE IV GX FPGA 75K 484FBG |
| M24308/4-261 | CONN D-SUB HOUSING PLUG 25POS |
| M24308/2-283 | CONN D-SUB HOUSING RECEPT 25POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX36-FPQ240 | 功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-FPQG208 | 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-FPQG240 | 功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-PQ208 | 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-PQ208A | 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
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