参数资料
| 型号： | A42MX36-FPQ208 |
| 厂商： | Microsemi SoC |
| 文件页数： | 76/142页 |
| 文件大小： | 0K |
| 描述： | IC FPGA MX SGL CHIP 54K 208-PQFP |
| 标准包装： | 24 |
| 系列： | MX |
| RAM 位总计： | 2560 |
| 输入/输出数： | 176 |
| 门数： | 54000 |
| 电源电压： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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40MX and 42MX FPGA Families
Re vi s i on 11
1 - 35
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing
tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as
the length of routing tracks, the number of interconnect elements, or the number of inputs increases.
From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing
tracks.
The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the
delay of the interconnect elements and by decreasing the number of interconnect elements per path.
Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses,
fabricated in 0.45 m lithography, offer nominal levels of 100
Ω resistance and 7.0 fF capacitance per
antifuse.
MX fanout distribution is also tight due to the low number of antifuses required for each interconnect
path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, and design-
dependent. The input and output buffer characteristics are common to all MX devices. Internal routing
delays are device-dependent; actual delays are not determined until after place-and-route of the user's
design is complete. Delay values may then be determined by using the Designer software utility or by
performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment in Microsemi's Designer software prior to placement and routing.
Up to 6% of the nets in a design may be designated as critical.
Long Tracks
Some nets in the design use long tracks, which are special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and sometimes four antifuse connections, which
increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks.
Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add
approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section, shown in Table 1-28 on page 1-40.
Timing Derating
MX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature and worst-case processing.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-FPQG208 | IC FPGA MX SGL CHIP 54K 208-PQFP |
| EP4CGX75CF23I7 | IC CYCLONE IV GX FPGA 75K 484FBG |
| EP4CGX75CF23C6 | IC CYCLONE IV GX FPGA 75K 484FBG |
| M24308/4-261 | CONN D-SUB HOUSING PLUG 25POS |
| M24308/2-283 | CONN D-SUB HOUSING RECEPT 25POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX36-FPQ240 | 功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-FPQG208 | 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-FPQG240 | 功能描述:IC FPGA MX SGL CHIP 54K 240-PQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-PQ208 | 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| A42MX36-PQ208A | 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
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