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参数资料
| 型号： | A42U2604SERIES |
| 英文描述： | 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
| 中文描述： | 4米× 4的CMOS动态RAM与江户页面模式 |
| 文件页数： | 10/25页 |
| 文件大小： | 413K |
| 代理商： | A42U2604SERIES |
A42U2604 Series
PRELIMINARY (June, 2001, Version 0.0)
9
AMIC Technology, Inc.
Notes:
1. I
CC1
, I
CC3
, I
CC4
, and I
CC5
depend on cycle rate.
2. I
CC1
and I
CC4
depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200
μ
s is required after power-up followed by any 8
RAS
cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8
CAS
-before-
RAS
initialization cycles instead of 8
RAS
cycles are required. 8 initialization cycles are required after extended periods of bias without.
4. AC Characteristics assume t
T
= 2ns. All AC parameters are measured with a load equivalent to one TTL load and
100pF, V
IL
(min.)
≥
GND and V
IH
(max.)
≤
VCC.
5. V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Transition times are measured
between V
IH
and V
IL
.
6. Operation within the t
RCD
(max.) limit insures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference
point only. If t
RCD
is greater than the specified t
RCD
(max.) limit, then access time is controlled exclusively by t
CAC
.
7. Operation within the t
RAD
(max.) limit insures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference
point only. If t
RAD
is greater than the specified t
RAD
(max.) limit, then access time is controlled exclusively by t
AA
.
8. Assumes three state test load (5pF and a 500
Thevenin equivalent).
9. Either t
RCH
or t
RRH
must be satisfied for a read cycle.
10. t
OFF
(max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. t
WCS
, t
WCH
, t
RWD
, t
CWD
and t
AWD
are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If t
WCS
≥
t
WCS
(min.) and t
WCH
≥
t
WCH
(min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If t
RWD
≥
t
RWD
(min.) , t
CWD
≥
t
CWD
(min.) and t
AWD
≥
t
AWD
(min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. Access time is determined by the longer of t
AA
or t
CAC
or t
CPA
.
13. t
ASC
≥
t
CP
to achieve t
PC
(min.) and t
CPA
(max.) values.
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相关代理商/技术参数 |
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| A42U2604V | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
| A42U2604V-50 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
| A42U2604V-50U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
| A42U2604V-60 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
| A42U2604V-60U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE |
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