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| 型号： | A4402KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/17页 |
| 文件大小： | 0K |
| 描述： | IC REG DL BUCK/LINEAR 16-TSSOP |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）（1），线性（LDO）（1） |
| 功能： | 车载 |
| 输出数： | 2 |
| 频率 - 开关： | 2MHz |
| 电压/电流 - 输出 1： | 3.3 V ~ 5 V，1A |
| 电压/电流 - 输出 2： | 1.8 V ~ 3.3 V，250mA |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 6 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 16-TSSOP-EP |
| 包装： | 标准包装 |
| 其它名称： | 620-1462-6 |
A4402
Constant On-Time Buck Converter
With Integrated Linear Regulator
supply voltage and maximum load. For supply voltages below V IN1 – V OUT 1
× DC ×
L =
where I RIPPLE is 25% of the maximum load current, and f SW (min)
Output Capacitor The converter is designed to operate with
a low-value ceramic output capacitor. When choosing a ceramic
capacitor, make sure the rated voltage is at least 3 times the
maximum output voltage of the converter. This is because the
capacitance of a ceramic decreases as they operate closer to their
on-time, so the complete formula should be used to make sure the
converter does not violate the timing specification.
running at frequencies above 2 MHz. This makes it possible to I RIPPLE
V RIPPLE =
use small inductor values, which reduces cost and board area.
exceed the minimum on-time or minimum off-time of the con- Using the duty cycle, a ripple current can be calculated using the
verter. The minimum on-time occurs at maximum input voltage following formula:
and minimum load. The maximum off-time occurs at minimum
, (20)
9.5 V and above 17 V, refer to the Low and High Voltage Opera - I RIPPLE f SW (min)
tion section.
Low and High Voltage Operation The converter can run at is the minimum switching frequency (nominal frequency minus
very low input voltages. With a 5 V output, the minimum input 25%). For the example used above, a 1 A converter with a supply
supply can be as low as 6 V. When operating at high frequencies, voltage of 13.5 V was the design objective. The supply voltage
the on-time of the converter must be very short because the avail- can vary by ±10%. The output voltage is 5 V, V f is 0.5 V, V SENSE
able period is short. At high input voltages the converter must is 0.15, and the desired frequency is 2.0 MHz. The duty cycle
maintain very short on-times, while at low input voltages the con- is calculated to be 36.45%. The worst-case frequency is 2 MHz
verter must maintain long off-times. Rather than limit the supply minus 20% or 1.6 MHz. Using these numbers in the above
voltage range, the converter solves this problem by automatically formula shows that the minimum inductance for this converter is
increasing the period by a factor of 3.5. With the period extended, 9.6 μH.
the converter will not violate the minimum on-time or off-time.
If the input voltage is between 9.5 V and 17 V, the converter will
maintain a constant period. When calculating worst-case on-times
and off-times, make sure to use the multiplier if the supply volt-
age is between those values.
When operating at voltages below 8 V, additional care must be rated voltage. It is recommended that the output be decoupled
taken when selecting the inductor and diode. At low voltages with a 10 μF, X7R ceramic capacitor. Larger capacitance may be
the maximum current may be limited due to the IR drops in the required on the outputs if load surges dramatically influence the
current path. When selecting external components for low voltage output voltage.
operation, the IR drops must be considered when determining
Output ripple is determined by the output capacitance and the
effects of ESR and ESL can be ignored assuming recommended
layout techniques are followed. The output voltage ripple is
Inductor Selection Choosing the right inductor is critical to approximated by:
the correct operation of the switcher. The converter is capable of
. (21)
4 × f SW × C OUT
V SW + V f + ( R SENSE × I PEAK ) (19)
DC =
V IN1 (max) + V f + ( R SENSE × I PEAK )
Theinductorvalueiswhatdeterminestheripplecurrent.Itis
important to size the inductor so that under worst-case conditions
I VALLEY equals I AV minus half the ripple current plus reasonable
margin. If the ripple current is too large, the converter will be
current limited. Typically peak-to-peak ripple current should be
limited to 20% to 25% of the maximum average load current.
Worst-case ripple current occurs at maximum supply voltage.
After calculating the duty cycle, DC, for this condition, the ripple
current can be calculated. First to calculate DC:
.
Input Capacitor The value of the input capacitance affects
the amount of current ripple on the input. This current ripple is
usually the source of supply side EMI. The amount of interfer-
ence depends on the impedance from the input capacitor and
the bulk capacitance located on the supply bus. Adding a small
value, 0.1 μF , ceramic capacitor as close to the input supply pin
as possible can reduce EMI effects. The small capacitor will help
reduce high frequency transient currents on the supply line. If
further filtering is needed it, is recommended that two ceramic
capacitors be used in parallel to further reduce emissions.
Rectification Diode The diode conducts the current during the
off-cycle. A Schottky diode is needed to minimize the forward
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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