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参数资料
| 型号： | A4936METTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/9页 |
| 文件大小： | 0K |
| 描述： | IC DC MOTOR PREDRIVER 3PH 32QFN |
| 标准包装： | 1 |
| 应用： | DC 电机驱动器，无刷（BLDC），3 相 |
| 输出数： | 1 |
| 工作温度： | -20°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 其它名称： | 620-1347-6 |
A4936
3-Phase Brushless DC Motor Pre-Driver
Overvoltage Protection VBB is monitored to determine if a
hazardous voltage is present due to the motor generator pump-
ing up the supply bus. When the voltage exceeds V BBOV , the
synchronous rectification feature is disabled.
Overtemperature Protection If die temperature exceeds
approximately 165°C, the Thermal Shutdown function will dis-
able the outputs until the internal temperature falls below the
threshold, by the hysteresis.
Lock Detect Function The A4936 monitors the Hall inputs
and the control inputs to determine if a locked rotor condition is
present. A locked rotor is determined to be present under either of
these two different conditions:
? The Hall inputs are not consistently changing.
? The proper commutation sequence is not being followed. The
motor can be locked in a condition in which it toggles between
two specific Hall device states.
If there are no Hall input changes within the lock time, t lock , or
the Hall inputs toggle between two adjacent states for longer then
t lock , then the outputs are disabled, and the fault is latched.
The fault remains latched until cleared by any one of the follow-
ing actions:
? Rising or falling edge on the DIR pin.
? VBB UVLO threshold exceeded (during power-up cycle).
? PWM pin held low for > t lock / 2.
The lock time, t lock , is set by a capacitor connected to the CLD
pin. C LD produces a triangle waveform (1.67 V peak-to-peak)
with frequency linearly related to the capacitor value. t lock is
defined as 127 cycles of this triangle waveform, or:
t lock = C LD × 20
where:
t lock is the lock time in seconds, and
C LD is the value of the capacitor in μ F.
The Lock Detect function is disabled by connecting CLD to
GND.
When BRAKE is high, lock detection is disabled. It also is dis-
abled if the PWM input remains low for the duration of the Hall
input lock detection.
FG Amplifier and Comparator A differential amplifier and
a comparator are integrated into the A4936 to amplify and shape
the FG signal from the FG coil underneath the motor. This coil
is typically created with a copper PCB trace, and as the motor
spins, the coil creates a low amplitude sinusoidal voltage with a
frequency proportional to the motor speed.
The FG input differential amplifier is biased at 2.5 V, and the gain
is set by the impedance between the FGFB pin and the FG– input.
This amplified signal is then compared to 2.5 V to create the
FGS output signal. The recommended value for the gain setting
feedback resistor is 50 to 500 k Ω . The recommended value for
the capacitor between FB+ and GND is 10 nF to 10 μ F.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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