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| 型号： | A4938EETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/10页 |
| 文件大小： | 0K |
| 描述： | IC DC MOTOR PREDRIVER 3PH 28-QFN |
| 标准包装： | 1 |
| 应用： | DC 电机控制器，无刷（BLDC），3 相 |
| 输出数： | 1 |
| 电源电压： | 8.5 V ~ 30 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN |
| 包装： | 标准包装 |
| 其它名称： | 620-1383-6 |
A4938
3-Phase Brushless DC Motor Pre-Driver
holding ENABLE high for longer than 3 ms. Note that the state
of BRAKEZ does not affect Standby mode.
Charge Pump The internal charge pump is used to generate a
supply above V BB to drive the high-side MOSFETs. The voltage
on the VCP pin is internally monitored, and in the case of a fault
condition, the outputs of the device are disabled.
Fault Shutdown In the event of a fault due to excessive
junction temperature, or due to low voltage on VCP or VBB,
the outputs of the device are disabled until the fault condition is
removed. At power-up the UVLO circuit disables the drivers.
Overvoltage Protection VBB is monitored to determine if
a hazardous voltage is present due to the motor generator pump-
ing-up the supply bus. When the voltage exceeds V BBOV , the
synchronous rectification feature is disabled. Connecting OVP to
GND sets V BBOV to 16 V typically, and leaving OVP open sets
V BBOV to 29 V typically.
Overtemperature Protection If die temperature exceeds
approximately 170°C, the Thermal Shutdown function will dis-
able the outputs until the internal temperature falls below the
threshold hysteresis.
Hall State Reporting The FG1 pin is an open drain output
that changes state at each transition of an external Hall element.
Lock Detect Function The IC will evaluate a locked rotor
condition under either of these two different conditions:
? The FG1 signal is not consistently changing.
? The proper commutation sequence is not being followed. The
motor can be locked in a condition in which it toggles between
two specific Hall device states.
Both of these fault conditions are allowed to persist for a period
of time, t lock . The value of t lock is set by capacitor connected to
the CLD pin. C LD produces a triangle waveform (1.67 V peak-to-
peak) with a frequency linearly related to the capacitor value. t lock
is defined as 127 cycles of this triangle waveform, or:
t lock = C LD × 20 s/ μ F
After the wait time, t lock , has expired, the outputs are disabled,
and the fault is latched.
These fault conditions are latched and can only be cleared by any
one of the following actions:
? Rising or falling edge on the DIR pin
? VBB UVLO threshold exceeded (during power-up cycle)
? ENABLE pin held high for > t lock / 2
The Lock Detect function can be disabled by connecting CLD to
GND.
When the A4938 is in Brake mode, the Lock Detect counter is
disabled.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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