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| 型号： | A4973SLBTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC PWM MOTOR DVR FULL 16SOIC |
| 特色产品： | A4973 Motor Driver |
| 标准包装： | 1 |
| 应用： | 直流电机驱动器，PWM 电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | 1.5A |
| 电压 - 负载： | 5 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 标准包装 |
| 其它名称： | 620-1438-6 |
A4973
PWM of the PHASE and ENABLE Inputs. The
PHASE and ENABLE inputs can be pulse-width modulated
to regulate load current. If the internal PWM current control is
used, the comparator blanking function is active during phase
and enable transitions. This eliminates false tripping of the
over-current comparator caused by switching transients (see RC
Blanking section, above).
Enable PWM. With the MODE input low, toggling the
ENABLE input turns on and off the selected source and sink
drivers. The corresponding pair of intrinsic flyback and ground-
clamp diodes conduct after the drivers are disabled, resulting
in fast current decay. When the device is enabled the internal
current-control circuitry will be active and can be used to limit
the load current in a slow current-decay mode.
For applications that PWM the ENABLE input and desire the
internal current-limiting circuit to function in the fast decay
mode, the ENABLE input signal should be inverted and
connected to the MODE input. This prevents the device from
being switched into sleep mode when the ENABLE input is low.
Phase PWM. Toggling the PHASE terminal selects which
sink/source pair is enabled, producing a load current that varies
with the duty cycle and remains continuous at all times. This
can have added benefits in bidirectional brush dc servo motor
applications as the transfer function between the duty cycle on
the PHASE input and the average voltage applied to the motor is
more linear than in the case of ENABLE PWM control (which
produces a discontinuous current at low current levels). For more
information see DC Motor Applications section, below.
Synchronous Fixed-Frequency PWM. The internal
PWM current-control circuitry of multiple A4973 devices can
be synchronized by using the simple circuit shown in figure 3.
A 555 IC can be used to generate the reset pulse/blanking signal
(t 1 ) for the device and the period of the PWM cycle (t 2 ). The
value of t 1 should be a minimum of 1.5 ms. When used in this
configuration, the R T and C T components should be omitted. The
PHASE and ENABLE inputs should not be PWMed with this
circuit configuration due to the absence of a blanking function
synchronous with their transitions.
Miscellaneous Information. A logic high applied to both
the ENABLE and MODE terminals puts the device into a sleep
Full-Bridge PWM Motor Driver
only to protect the device from failures due to excessive junction
temperatures and should not imply that output short circuits
are permitted. The hysteresis of the thermal shutdown circuit is
approximately 15°C.
APPLICATION NOTES
Current Sensing. The actual peak load current (I PEAK ) will
be above the calculated value of I TRIP due to delays in the turn
off of the drivers. The amount of overshoot can be approximated
by:
(V BB – [(I TRIP x R LOAD ) + V BEMF ]) x t PWM(OFF)
I OS ≈
L LOAD
where V BB is the motor supply voltage, V BEMF is the back-EMF
voltage of the load, R LOAD and L LOAD are the resistance and
inductance of the load respectively, and t PWM(OFF) is specified in
the electrical characteristics table.
The reference terminal has a maximum input bias current
of ±5 μ A. This current should be taken into account when
determining the impedance of the external circuit that sets the
reference voltage value.
To minimize current-sensing inaccuracies caused by ground
trace I x R drops, the current-sensing resistor should have a
separate return to the ground terminal of the device. For low-
value sense resistors, the I x R drops in the printed wiring board
can be significant and should be taken into account. The use of
sockets should be avoided as their contact resistance can cause
variations in the effective value of R S .
Generally, larger values of R S reduce the aforementioned effects
but can result in excessive heating and power loss in the sense
resistor. The selected value of R S should not cause the absolute
maximum voltage rating of 500 mV, for the SENSE terminal, to
be exceeded.
Figure 3
Synchronous Fixed-Frequency Control Circuit
V CC
mode to minimize current consumption when not in use.
An internally generated dead time prevents crossover currents
that can occur when switching phase or braking.
t
2
1N4001
RC 1
Thermal protection circuitry turns off all drivers should the
junction temperature reach 165°C (typical). This is intended
t
1
2N2222
RC N
Dwg. EP-060
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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