参数资料
型号: A4986SLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 7/17页
文件大小: 0K
描述: IC PWM MOTOR DRIVER 24TSSOP
特色产品: A498x Motor Driver Family
标准包装: 1
应用: PWM 电机驱动器
评估套件: 可供
输出数: 1
电流 - 输出: ±2A
电压 - 负载: 8 V ~ 35 V
电源电压: 3 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 24-TSSOP 裸露焊盘
包装: 标准包装
其它名称: 620-1342-6
A4986
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
source-side FET gates. A 0.1 μ F ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μ F ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
V REG (VREG) . This internally-generated voltage is used to
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled
with a 0.22 μ F ceramic capacitor to ground. V REG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4986 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
5 A / div.
t →
Figure 1. Short-to-ground event
Fault
latched
Shutdown. In the event of a fault, overtemperature (excess T J )
or an undervoltage (on VCP), the FET outputs of the A4986 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode ( ˉSˉ ˉLˉ ˉEˉ ˉEˉ ˉPˉ ). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator, and
charge pump. A logic low on the SLEEP pin puts the A4986 into
Sleep mode. When emerging from Sleep mode, in order to allow
the charge pump to stabilize, provide a delay of 1 ms before issu-
ing a logic command.
Mixed Decay Operation. The bridge operates in Mixed
Decay mode, as shown in figures 5 through 7. As the trip point
5 A / div.
Fixed off-time
t →
Figure 2. Shorted load (OUTxA → OUTxB) in
Slow decay mode
is reached, the A4986 initially goes into a fast decay mode for
31.25% of the off-time, t OFF . After that, it switches to Slow Decay
mode for the remainder of t OFF . A timing diagram for this feature
appears in figure 4.
Synchronous Rectification . When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recir-
culates in Mixed Decay mode. This synchronous rectification
5 A / div.
Fixed off-time
feature turns on the appropriate FETs during current decay, and
effectively shorts out the body diodes with the low FET R DS(ON) .
This reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications. Syn-
chronous rectification turns off when the load current approaches
zero (0 A), preventing reversal of the load current.
Fast decay portion
(direction change)
t →
Figure 3. Shorted load (OUTxA → OUTxB) in Mixed decay mode
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
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