参数资料
型号: A54SX08A-FG144A
厂商: Microsemi SoC
文件页数: 63/108页
文件大小: 0K
描述: IC FPGA SX 12K GATES 144-FBGA
标准包装: 160
系列: SX-A
LAB/CLB数: 768
输入/输出数: 111
门数: 12000
电源电压: 2.25 V ~ 5.25 V
安装类型: 表面贴装
工作温度: -40°C ~ 125°C
封装/外壳: 144-LBGA
供应商设备封装: 144-FPBGA(13x13)
SX-A Family FPGAs
2- 38
v5.3
Table 2-31 A54SX32A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 4.75 V, TJ = 70°C)
Parameter
Description
–3 Speed*
–2 Speed
–1 Speed
Std. Speed
–F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-cell Input)
1.7
1.9
2.2
2.6
4.0
ns
tHCKL
Input High to Low
(Pad to R-cell Input)
1.7
2.0
2.2
2.6
4.0
ns
tHPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tHPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tHCKSW
Maximum Skew
0.6
0.7
0.8
1.3
ns
tHP
Minimum Period
2.8
3.2
3.6
4.2
5.8
ns
fHMAX
Maximum Frequency
357
313
278
238
172
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (Light Load)
(Pad to R-cell Input)
2.2
2.5
2.8
3.3
4.7
ns
tRCKL
Input High to Low (Light Load)
(Pad to R-cell Input)
2.1
2.5
2.8
3.3
4.5
ns
tRCKH
Input Low to High (50% Load)
(Pad to R-cell Input)
2.4
2.7
3.1
3.6
5.1
ns
tRCKL
Input High to Low (50% Load)
(Pad to R-cell Input)
2.2
2.6
2.9
3.4
4.7
ns
tRCKH
Input Low to High (100% Load)
(Pad to R-cell Input)
2.5
2.8
3.2
3.8
5.3
ns
tRCKL
Input High to Low (100% Load)
(Pad to R-cell Input)
2.4
2.8
3.1
3.7
5.2
ns
tRPWH
Minimum Pulse Width High
1.4
1.6
1.8
2.1
2.9
ns
tRPWL
Minimum Pulse Width Low
1.4
1.6
1.8
2.1
2.9
ns
tRCKSW
Maximum Skew (Light Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (50% Load)
1.0
1.1
1.3
1.5
2.1
ns
tRCKSW
Maximum Skew (100% Load)
1.0
1.1
1.3
1.5
2.1
ns
Note: *All –3 speed grades have been discontinued.
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