参数资料
型号: A6281EESTR-T
厂商: Allegro Microsystems Inc
文件页数: 4/11页
文件大小: 0K
描述: IC LED DRIVER PWM CONTROL 16-QFN
产品培训模块: A6281 Three-channel LED Driver
标准包装: 1,500
恒定电流:
拓扑: 线性,PWM
输出数: 3
内部驱动器:
类型 - 次要: RGB
频率: 5MHz
电源电压: 4.75 V ~ 17 V
输出电压: 1 V ~ 3 V
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-QFN/MLP 裸露焊盘(3x3)
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
产品目录页面: 1141 (CN2011-ZH PDF)
其它名称: 620-1218-2
A6281
3-Channel Constant Current LED Driver
with Programmable PWM Control
OPERATING CHARACTERISTICS , valid at T A = 25°C, V IN = 4.75 to 17.0 V, unless otherwise noted
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
ELECTRICAL CHARACTERISTICS
Quiescent Supply Current
Operating Supply Current
Load Supply Voltage
Undervoltage Lockout
VREG Voltage Range 1
Output Current (any single output)
I DD
I DD
V IN
V IN(UV)
V REG
I OUT
f CLKIN = 0.0 Hz
f CLKIN = 5 MHz
V IN rising
V IN falling
I OUT =15 mA, V IN = 17 V
R EXT = 5 k Ω , scalar = 100%
R EXT = 15 k Ω , scalar = 100%
4.75
3.0
4.6
135
45
150.0
51
5.0
15.0
17
4.5
5.4
165
57
mA
mA
V
V
V
V
mA
mA
Output to Output Matching
Error 2
Err
Output to output variation—all outputs on, R EXT = 5 k Ω
–7
7
%
Output Voltage Range
Load Regulation (I %Diff / ? V DS )
V DS(min)
R EXT = 5 k Ω , V DS = 1 to 3 V
1.0
±1
3.0
±3
V
%/V
Output Leakage Current
I DSX
V OH = 17 V
1.0
μ A
Logic Input Voltage
Logic Input Voltage Hysteresis
V IH
V IL
All digital inputs
2.0
150
0.8
V
V
mV
CI and SDI Pins Logic Input Current
Input Resistance
Logic Output Voltage
I IN
R I
V OL
V OH
V IN = 0 to 5 V
OEI pin, pull-up
LI pin, pull-down
V IN ≥ 5.0 V, I O = ±2 mA
–20
150
100
3.8
300
200
20
600
400
0.4
μ A
k Ω
k Ω
V
V
Output Dot Correction Error
PWM Oscillator
f PWM
R EXT = 5 k Ω ; LSB
±1
800
bit
kHz
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T JTSD
T Jhys
Temperature increasing
165
15
°C
°C
SWITCHING CHARACTERISTICS
Clock Hold Time
Data Setup Time
Data Hold Time
Latch Setup Time 3
Latch Hold Time
Output Enable Set Up Time
Output Enable Falling to Outputs Turning On
Propagation Delay Time
t H(CLK)
t SU(D)
t H(D)
t SU(LI)
t H(LI)
t SU(OE)
t P(OE)
20
20
20
20
20
40
200
ns
ns
ns
ns
ns
ns
ns
Clock to Output Propagation Delay Time
Logic Output Fall Time
Logic Output Rise Time
Output Fall Time (Turn Off)
Output Rise Time (Turn On)
Clock Falling Edge to Serial Data Out
Propagation Delay Time
Logic In to Output Propagation Delay
Clock Out Pulse Duration
Maximum Clock In Frequency
t P(OUT)
t BF
t BR
t f
t r
t P(SDO)
t P(IO)
t w(CLK)
f CI
External clock selected, V DS = 1.0 V, I O = 150 mA
C OB = 50 pF, 4.5 to 0.5 V
C OB = 50 pF, 0.5 to 4.5 V
C OUT = 10 pF, 90% to 10% of I OUT = 10 mA
C OUT = 10 pF, 90% to 10% of I OUT = 150 mA
C OUT = 10 pF, 10% to 90% of I OUT = 10 mA
C OUT = 10 pF, 10% to 90% of I OUT = 150 mA
LI → LO, CI → CO, OEI → OEO
70
200
50
30
10
10
50
100
50
50
100
100
60
130
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
1 If V IN is a 4.75 to 5.5 V supply, connect VIN to VREG externally
2 Err = [I O (min or max) – I O (av)] / I O (av), where I O (av) = average of 3 output current values.
3 In daisy-chained applications, t SU(LI) must be increased for the quantity of pixels in the chain (see Application Information section).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
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