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参数资料
| 型号： | A6595KLWTR |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 7/10页 |
| 文件大小： | 0K |
| 描述： | IC PWR DRIVER 8BIT SER 20-SOIC |
| 标准包装： | 1,000 |
| 类型： | 高端 |
| 输入类型： | 非反相 |
| 输出数： | 8 |
| 导通状态电阻： | 1.3 欧姆 |
| 电流 - 输出 / 通道： | 250mA |
| 电流 - 峰值输出： | 750mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
A6595
8-Bit Serial Input DMOS Power Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V DD and Ground)
C
CLOCK
A
50%
B
SERIAL
DATA N I
DATA
t p
50%
SERIAL
DATA OUT
STROBE
OUTPUT
D
50%
50%
E
DATA
ENABLE
LOW = ALL OUTPUTS ENABLED
t p
HI
GH = OUTPUTOFF
OU T N
50%
DATA
LOW = OUTPUT N O
Dwg. WP-029-2
HIGH = ALL OUTPUTS DISABLED
OUTPUT
ENABLE
50%
t PLH
OU T N
t PHL
90%
t f
DATA
t r
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t su(D) .......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), t h(D) .............................................. 10 ns
C. Clock Pulse Width, t w(CLK) ............................................. 20 ns
D. Time Between Clock Activation
and Strobe, t su(ST) ....................................................... 50 ns
E. Strobe Pulse Width, t w(ST) ............................................... 50 ns
F. Output Enable Pulse Width, t w(OE) ................................ 4.5 μ s
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift reg-
ister on the rising edge of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With the
OUTPUT ENABLE input low, the outputs are controlled by the
state of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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