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参数资料
| 型号： | A6595KLWTR |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/10页 |
| 文件大小： | 0K |
| 描述： | IC PWR DRIVER 8BIT SER 20-SOIC |
| 标准包装： | 1,000 |
| 类型： | 高端 |
| 输入类型： | 非反相 |
| 输出数： | 8 |
| 导通状态电阻： | 1.3 欧姆 |
| 电流 - 输出 / 通道： | 250mA |
| 电流 - 峰值输出： | 750mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
A6595
8-Bit Serial Input DMOS Power Driver
TERMINAL DESCRIPTIONS
Terminal No.
1
2
3
4-7
8
9
10
11
12
13
14-17
18
19
20
Terminal Name
POWER GROUND
LOGIC SUPPLY
SERIAL DATA IN
OUT 0-3
CLEAR
OUTPUT ENABLE
POWER GROUND
POWER GROUND
STROBE
CLOCK
OUT 4-7
SERIAL DATA OUT
LOGIC GROUND
POWER GROUND
Function
Reference terminal for output voltage measurements (OUT 0-3 ).
(V DD ) The logic supply voltage (typically 5 V).
Serial-data input to the shift-register.
Current-sinking, open-drain DMOS output terminals.
When (active) low, the registers are cleared (set low).
When (active) low, the output drivers are enabled; when high, all output driv-
ers are turned OFF (blanked).
Reference terminal for output voltage measurements (OUT 0-3 ).
Reference terminal for output voltage measurements (OUT 0-7 ).
Data strobe input terminal; shift register data is latched on rising edge.
Clock input terminal for data shift on rising edge.
Current-sinking, open-drain DMOS output terminals.
CMOS serial-data output to the following shift register.
Reference terminal for input voltage measurements.
Reference terminal for output voltage measurements (OUT 4-7 ).
NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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