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| 型号： | A80960HA25SL2GX |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor |
| 中文描述： | 32-BIT, 25 MHz, RISC PROCESSOR, CPGA168 |
| 封装： | PGA-168 |
| 文件页数： | 36/102页 |
| 文件大小： | 828K |
| 代理商： | A80960HA25SL2GX |
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80960HA/HD/HT
30
Advance Information
Datasheet
4.3
Recommended Connections
Power and ground connections must be made to multiple V
CC
and V
SS
(GND) pins. Every
80960Hx-based circuit board should include power (V
CC
) and ground (V
SS
) planes for power
distribution.EveryV
CC
pinmust beconnected to thepowerplane;every V
SS
pinmustbeconnectedto
the ground plane. Pins identified as “NC” —no connect pins—
must not
be connected in the system.
Liberaldecouplingcapacitanceshouldbeplacednearthe80960Hx.Theprocessorcancausetransient
power surges when its output buffers transition, particularly when connected to large capacitive loads.
Low inductance capacitors and interconnects are recommended for best high-frequency electrical
performance. Inductance can be reduced by shortening the board traces between the processor and
decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages
offer the lowest possible inductance.
For reliable operation, always connect unused inputs to an appropriate signal level. In particular,
any unused interrupt (XINT7:0, NMI) input should be connected to V
CC
through a pull-up resistor,
as should BTERM if not used. Pull-up resistors should be in the range of 20 K
for each pin tied
high. If READY or HOLD are not used, the unused input should be connected to ground.
N.C. pins
must always remain unconnected.
4.4
VCC5 Pin Requirements (V
DIFF
)
In mixed-voltage systems that drive 80960Hx processor inputs in excess of 3.3 V, the VCC5 pin must
be connected to the system’s 5 V supply. To limit current flow into the VCC5 pin, there is a limit to
the voltage differential between the VCC5 pin and the other V
CC
pins. The voltage differential
between the 80960Hx VCC5 pin and its 3.3 V V
CC
pins should never exceed 2.25 V. This limit
applies to power-up, power-down, and steady-state operation.
Table 20
outlines this requirement.
Meeting this requirement ensures proper operation and guarantees that the current draw into the
VCC5 pin does not exceed the I
CC5
specification.
If the voltage difference requirements cannot be met due to system design limitations, an alternate
solution may be employed. As shown in
Figure 7
, a minimum of 100
series resistor may be used
to limit the current into the VCC5 pin. This resistor ensures that current drawn by the VCC5 pin
does not exceed the maximum rating for this pin.
This resistor is not necessary in systems that can guarantee the V
DIFF
specification.
In 3.3 V-only systems and systems that drive 80960Hx pins from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V V
CC
plane.
Figure 7. VCC5 Current-Limiting Resistor
+5 V (±0.25 V)
VCC5 Pin
100
(±5%, 0.5 W)
Table 20. V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Sym
Parameter
Min
Max
Units
Notes
V
DIFF
VCC5-V
Difference
2.25
V
VCC5 input should not exceed V
by more than 2.25 V during
power-up and power-down, or during steady-state operation.
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| A80960HA33SL2GY | 功能描述:IC MPU I960HA 3V 33MHZ 168-PGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:40 系列:MPC83xx 处理器类型:32-位 MPC83xx PowerQUICC II Pro 特点:- 速度:267MHz 电压:0.95 V ~ 1.05 V 安装类型:表面贴装 封装/外壳:516-BBGA 裸露焊盘 供应商设备封装:516-PBGAPGE（27x27） 包装:托盘 |
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| A80960HA40SL2GZ | 功能描述:IC MPU I960HA 3V 40MHZ 168-PGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
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