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| 型号： | A80960JT-75 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | EMBEDDED 32-BIT MICROPROCESSOR |
| 中文描述： | 32-BIT, 75 MHz, RISC PROCESSOR, CPGA132 |
| 封装： | PGA-132 |
| 文件页数： | 20/78页 |
| 文件大小： | 835K |
| 代理商： | A80960JT-75 |
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80960JA/JF/JD/JT 3.3 V Microprocessor
20
Advance Information Datasheet
Table 4.
Pin Description — Processor Control Signals, Test Signals and Power
NAME
TYPE
DESCRIPTION
CLKIN
I
CLOCK
INPUT
provides the processor’s fundamental time base; both the processor
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
RESET
I
A(L)
RESET
initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
During reset, the input pins are ignored with the exception of LOCK/ONCE, STEST
and HOLD.
The RESET pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET must be asserted a minimum of 10,000 CLKIN
cycles with V
CC
and CLKIN stable. On a warm reset, RESET should be asserted for
a minimum of 15 cycles.
STEST
I
S(L)
SELF TEST
enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
FAIL
O
R(0)
H(Q)
P(1)
FAIL
indicates a failure of the processor’s built-in self-test performed during
initialization. FAIL is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
When self-test passes, the processor deasserts FAIL and begins operation from
user code.
When self-test fails, the processor asserts FAIL and then stops executing.
0 = self test failed
1 = self test passed
TCK
I
TEST CLOCK
is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TDI
I
S(L)
TEST DATA INPUT
is the serial input pin for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
TDO
O
R(Q)
HQ)
P(Q)
TEST DATA OUTPUT
is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
TRST
I
A(L)
TEST RESET
asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and V
SS
. If TAP is not used,
this pin must be connected to V
SS
; however, no resistor is required. See Section 4.3,
“Connection Recommendations” on page 40.
TMS
I
S(L)
TEST MODE SELECT
is sampled at the rising edge of TCK to select the operation of
the test logic for IEEE 1149.1 Boundary Scan testing.
V
CC
–
POWER
pins intended for external connection to a V
CC
board plane.
VCCPLL
–
PLL POWER
is a separate V
CC
supply pin for the phase lock loop clock generator. It
is intended for external connection to the V
CC
board plane. In noisy environments,
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects
on timing relationships.
VCC5
–
5 V REFERENCE VOLTAGE
input is the reference voltage for the 5 V-tolerant I/O
buffers. This signal should be connected to +5 V for use with inputs which exceed
3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.
V
SS
NC
–
GROUND
pins intended for external connection to a V
SS
board plane.
–
NO CONNECT
pins. Do not make any system connections to these pins.
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