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参数资料
| 型号： | A80960JT-75 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | EMBEDDED 32-BIT MICROPROCESSOR |
| 中文描述： | 32-BIT, 75 MHz, RISC PROCESSOR, CPGA132 |
| 封装： | PGA-132 |
| 文件页数： | 40/78页 |
| 文件大小： | 835K |
| 代理商： | A80960JT-75 |
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80960JA/JF/JD/JT 3.3 V Microprocessor
40
Advance Information Datasheet
4.3
Connection Recommendations
For clean on-chip power distribution, V
CC
and V
SS
pins separately feed the device’s functional units.
Power and ground connections must be made to all 80960Jx power and ground pins. On the circuit board,
every V
CC
pin should connect to a power plane and every V
SS
pin should connect to a ground plane. Place
liberal decoupling capacitance near the 80960Jx, since the processor can cause transient power surges.
Pay special attention to the Test Reset (TRST) pin. It is essential that the JTAG Boundary Scan Test Access
Port (TAP) controller initializes to a known state whether it will be used or not. If the JTAG Boundary Scan
function will be used, connect a pulldown resistor between the TRST pin and V
SS
. If the JTAG Boundary
Scan function will not be used (even for board-level testing), connect the TRST pin to V
SS
.
Do not connect the TDI, TDO, and TCK pins if the TAP Controller will not be used.
Note:
Pins identified as NC must not be connected in the system
.
4.4
VCC5 Pin Requirements (VDIFF)
In 3.3 V only systems where the 80960Jx input pins are driven from 3.3 V logic, connect the VCC5
pin directly to the 3.3 V V
CC
plane.
In mixed voltage systems where the processor is powered by 3.3 V and interfaces with 5 V
components, VCC5 must be connected to 5 V. This allows proper 5 V tolerant buffer operation,
and prevents damage to the input pins. The voltage differential between the 80960Jx VCC5 pin and
its 3.3 V V
CC
pins must not exceed 2.25 V. If this requirement is not met, current flow through the
pin may exceed the value at which the processor is damaged. Instances when the voltage can
exceed 2.25 V is during power up or power down, where one source reaches its level faster than the
other, briefly causing an excess voltage differential. Another instance is during steady-state
operation, where the differential voltage of the regulator (provided a regulator is used) cannot be
maintained within 2.25 V. Two methods are possible to prevent this from happening:
Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V, or,
As shown in Figure 8, place a 100
resistor in series with the VCC5 pin to limit the current
through VCC5.
If the regulator cannot prevent the 2.25 V differential, the addition of the resistor is a simple and
reliable method for limiting current. The resistor can also prevent damage in the case of a power
failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
Figure 8.
VCC5 Current-Limiting Resistor
+5 V (±0.25 V)
VCC5 Pin
100
(±5%, 0.5 W)
Table 20.
VDIFF Parameters
Symbol
Parameter
Min
Max
Units
Notes
VDIFF
VCC5-V
CC
Difference
2.25
V
VCC5 input should not exceed V
by more than 2.25 V
during power-up and power-down, or during
steady-state operation.
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| A80960KA16 | 功能描述:IC MPU I960KA 16MHZ 132-PGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| A80960KA-16 | 制造商:Intel 功能描述: |
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| A80960KA25 | 功能描述:IC MPU I960KA 25MHZ 132-PGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:2 系列:MPC8xx 处理器类型:32-位 MPC8xx PowerQUICC 特点:- 速度:133MHz 电压:3.3V 安装类型:表面贴装 封装/外壳:357-BBGA 供应商设备封装:357-PBGA（25x25） 包装:托盘 |
| A80960KA-25 | 制造商:Intel 功能描述: |
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