参数资料
型号: A8285SLBTR-T
厂商: Allegro Microsystems Inc
文件页数: 13/18页
文件大小: 0K
描述: IC LNB SUPPLY/VOLTAGE REG 16SOIC
标准包装: 1
应用: 转换器,模拟和数字式卫星信号接收器
输入电压: 6 V ~ 16 V
输出数: 1
输出电压: 12.7 V ~ 20.4 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 标准包装
产品目录页面: 1141 (CN2011-ZH PDF)
其它名称: 620-1202-6
A8285 and
A8287
Example.
Given:
LNB Supply and Control Voltage Regulator
Layout Considerations
Recommended placement of critical components and tracking for
V IN = 12 V
V OUT = 18 V
I LOAD = 500 mA
Two-layer PCB.
Maximum ambient temperature = 70 oC,
Maximum allowed junction temperature= 110 oC
Assume:
V D = 0.4 V and select Δ V REG = 0.7 V
D = 1 – (12 / (18 + 0.4 + 0.7) = 0.37
I PK = 18 × 0.5 / (0.89 × 12) = 843 mA
R DSBOOST = 0.5 + (110 – 25) × 2.7 m Ω = 730 m Ω
Worst case losses can now be estimated:
Pd_Rds = 0.843 2 × 0.73 × 0.37 = 192 mW
Pd_sw = 70 mW
Pd_control = 15 mA × V IN = 180 mW
Pd_lin = 0.7 × 0.5 = 350 mW
and therefore
P TOT = 0.192 + 0.07 + 0.18 + 0.35 = 0.792 W
The thermal resistance required is:
(110 – 70) / 0.792 = 50.5oC/W
Note: For the case of the A8287, the area of copper required on
each layer is approximately 1.2 in 2 .
the A8287 is shown in the PCB Layout digagram on the follow-
ing page. It is recommended that the ground plane be separated
into two areas, referred to as switcher and control, on each layer
using a ground plane. With respect to the input connections, VIN
and 0V, the two ground plane areas are isolated as shown by the
dotted line and the ground plane areas are connected together at
pins 6, 7, 18, and 19. This configuration minimizes the effects of
the noise produced by the switcher on the noise-sensitive sections
of the circuit.
Power-related tracking from INPUT to L1, LNB (pin 17) to L2
then OUTPUT, LX (pin 20) to D1 and L1, VBOOST (pin 23)
to C4 and D1 should be as short and wide as possible. Power
components such as the boost diode D1, inductor L1, and input/
output capacitors C1, C9, and C4, should be located as close as
possible to the IC. The DiSEqC inductor L2 should be located as
far away from the boost inductor L1 to prevent potential magnetic
crosstalk.
The filter capacitor (VREG), charge pump capacitor (VCP),
ac coupling tone detect capacitor (TDI), tone pull-down resis-
tor (TOUT), and LNB output capacitor/protection diode (LNB)
should be located directly next to the appropriate pin.
Where a PCB with two or more layers is used, it is recommended
that four thermal vias be deployed as shown in the PCB Layout
diagram. Note that adding additional vias does not enhance the
thermal characteristics.
R ?JA vs. Area Charts
100
A8285, 16-Pin SOIC
80
A8287, 24-Pin SOIC
90
One side Copper
Two side Copper
70
One side Copper
Two side Copper
80
70
60
50
60
50
40
0
1
2
2 )
Area (in. 2 )
3
4
40
0
1
2
2 )
Area (in. 2 )
3
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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