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| 型号： | A8287SLBTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 5/18页 |
| 文件大小： | 0K |
| 描述： | IC LNB SUPPLY/VOLTAGE REG 24SOIC |
| 标准包装： | 1 |
| 应用： | 转换器，模拟和数字式卫星信号接收器 |
| 输入电压： | 9 V ~ 16 V |
| 输出数： | 1 |
| 输出电压： | 12.7 V ~ 20.4 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1200-6 |
A8285 and
A8287
LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS ( continued ) at T A = +25°C, V IN = 10 to 16 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Tone Characteristics
Tone Frequency
Tone Pull-Down Current
Tone Turn-On and Turn-Off Delays
External Tone Logic Input
Input Leakage
Tone Detector Input Amplitude
Tone Detector Frequency Capture
Tone Detector Input Impedance
Tone Detector Output Voltage
Tone Detector Output Leakage
f TONE
I TONE
t DEL
V IH
V IL
I IL
V TDI
f TDI
Z TDI
V OL
I OL
–
–
Using EXTM pin
–
–
–
f IN = 22 kHz
600 mV pp sinewave
See note 1
Tone present, I LOAD = 3 mA
Tone absent, V O = 7 V
20
30
–
2
–
–1
260
17.6
–
–
–
22
40
–
–
–
–
–
–
8.6
–
–
24
50
1
–
0.8
1
1000
26.4
–
0.4
10
kHz
mA
μ s
V
V
μ A
mV
kHz
k ?
V
? A
I 2 C Interface
Logic Input (SDA,SCL) Low Level
Logic Input (SDA,SCL) High Level
Input Hysteresis
Logic Input Current
Output Voltage (SDA, IRQ)
Output Leakage (SDA, IRQ)
SCL Clock Frequency
Output Fall Time
Bus Free Time Between Stop and Start
Hold Time for Start Condition
Setup Time for Start Condition
V IL
V IH
V HYS
I IN
V OL
I OL
f CLK
t OF
t BUF
t HD:STA
t SU:STA
–
–
–
V IN = 0 V to 7 V
I LOAD = 3 mA
V O = 0 V to 7 V
–
V IH to V IL
See I 2 C Interface Timing Diagram
See I 2 C Interface Timing Diagram
See I 2 C Interface Timing Diagram
–
2
–
–10
–
–
0
–
1.3
0.6
0.6
–
–
150
<±1.0
–
–
–
–
–
–
–
0.8
–
–
10
0.4
10
400
250
–
–
–
V
V
mV
μ A
V
μ A
kHz
ns
μ s
μ s
μ s
SCL Low Time
SCL High Time
t LOW
t HIGH
See
See
I 2 C
I 2 C
Interface Timing Diagram
Interface Timing Diagram
1.3
0.6
–
–
–
–
μ s
μ s
Data Setup Time
t SU:DAT
See
note1; I 2 C Interface Timing Diagram
100
–
–
ns
Data Hold Time
Setup Time for Stop Condition
t HD:DAT
t SU:STO
See
See
I 2 C
I 2 C
Interface Timing Diagram
Interface Timing Diagram
0
0.6
–
–
900
–
ns
μ s
Continued on next page
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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