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参数资料
| 型号： | A8287SLBTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/18页 |
| 文件大小： | 0K |
| 描述： | IC LNB SUPPLY/VOLTAGE REG 24SOIC |
| 标准包装： | 1 |
| 应用： | 转换器，模拟和数字式卫星信号接收器 |
| 输入电压： | 9 V ~ 16 V |
| 输出数： | 1 |
| 输出电压： | 12.7 V ~ 20.4 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1200-6 |
A8285 and
A8287
Timing Considerations
LNB Supply and Control Voltage Regulator
Application Information
time during a data transfer. The A8285/A8287 always responds by
The control sequence of the communication through the
I 2 C?-
resetting the data transfer sequence.
Compatible interface is composed of several steps in sequence:
1. Start Condition . Defined by a negative edge on the SDA line,
while SCL is high.
2. Address Cycle . 7 bits of address, plus 1 bit to indicate read
(1) or write (0), and an acknowledge bit. The first five bits of
the address are fixed as: 00010 . The four optional addresses,
defined by the remaining two bits, are selected by the ADD
input. The address is transmitted MSB first.
3. Data Cycles . 8 bits of data followed by an acknowledge bit.
Multiple data bytes can be read. Data is transmitted MSB first.
4. Stop Condition . Defined by a positive edge on the SDA line,
while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable
while the clock is high. SDA can only be changed while SCL is
low. It is possible for the Start or Stop condition to occur at any
The Read/Write bit is used to determine the data transfer direc-
tion. If the Read/Write bit is high, the master reads one or more
bytes from the A8285/A8287. If the Read/Write bit is low, the
master writes one byte to the A8285/A8287. Note that multiple
writes are not permitted. All write operations must be preceded
with the address.
The Acknowledge bit has two functions. It is used by the master
to determine if the slave device is responding to its address and
data, and it is used by the slave when the master is reading data
back from the slave. When the A8285/A8287 decodes the 7-bit
address field as a valid address, it responds by pulling SDA low
during the ninth clock cycle.
During a data write from the master, the A8285/A8287 also pulls
SDA low during the clock cycle that follows the data byte, in
order to indicate that the data has been successfully received. In
both cases, the master device must release the
Writing to the Register
acknowledge
from LNBR
acknowledge
from LNBR
Start
Address
W
Control Data
Stop
SDA
0
0
0
1
0
A1
A0
0
AK
D7
D6
D5
D4
D3
D2
D1
D0
AK
SCL
1
2
3
4
5
6
7
8
9
Reading One Byte from the Register
acknowledge
from LNBR
no acknowledge
from master
Start
Address
R
Status Data
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
Reading Multiple Bytes from the Register
acknowledge
from LNBR
acknowledge
from master
no acknowledge
from master
Start
Address
R
Status Data
Status Data
Stop
SDA
0
0
0
1
0
A1
A0
1
AK
D7
D6
D5
D4
D3
D2
D1
D0
AK
D7
D6
D5
D4
D3
D2
D1
D0 NAK
SCL
1
2
3
4
5
6
7
8
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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