- 您现在的位置：买卖IC网 > PDF目录375159 > A82DL3234TG-70IF (AMIC Technology Corporation) Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash PDF资料下载
参数资料
| 型号： | A82DL3234TG-70IF |
| 厂商： | AMIC Technology Corporation |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| 中文描述： | 堆叠式多芯片封装（MCP）闪存和SRAM，A82DL32x4T（ü）32兆位（4Mx8 Bit/2Mx16位）的CMOS 3.3伏只，同时闪电行动 |
| 文件页数： | 11/60页 |
| 文件大小： | 931K |
| 代理商： | A82DL3234TG-70IF |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
A82DL32x4T(U) Series
PRELIMINARY
(August, 2005, Version 0.0)
10
AMIC Technology, Corp.
Word/Byte Configuration
The
BYTE_F
pin determines whether the I/O pins I/O
15
-I/O
0
operate in the byte or word configuration. If the
BYTE_F
pin
is set at logic ”1”, the device is in word configuration, I/O
15
-
I/O
0
are active and controlled by
CE_F
and
OE
.
If the
BYTE_F
pin is set at logic “0”, the device is in byte
configuration, and only I/O
0
-I/O
7
are active and controlled by
CE_F
and
OE
. I/O
8
-I/O
14
are tri-stated, and I/O
15
pin is
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
CE_F
and
OE
pins to V
IL
.
CE_F
is the power control
and selects the device.
OE
is the output control and gates
array data to the output pins.
WE
should remain at V
IH
. The
BYTE_F
pin determines whether the device outputs array
data in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, l
CC1_F
in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
WE
and
CE_F
to V
IL
, and
OE
to V
IH
.
For program operations, the
BYTE_F
pin determines
whether the device accepts program data in bytes or words,
Refer to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
I
CC2_F
in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
the
WP
/ACC pin. This function is primarily intended to allow
faster manufacturing throughput at the factory.
If the system asserts V
HH
on this pin, the device automatically
enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing V
HH
from the
WP
/ACC pin returns the
device to normal operation. Note that the
WP
/ACC pin must
not be at V
HH
for operations other than accelerated program-
ming, or device damage may result. In addition, the
WP
/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O
7
-I/O
0
. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
Simultaneous Read/Write Operations with Zero
Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. I
CC6_F
and I
CC7_F
in the DC Characteristics
table represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
OE
input.
The device enters the CMOS standby mode when the
CE_F
&
RESET
pins are both held at VCC_F
±
0.3V. (Note
that this is a more restricted voltage range than V
IH
.) If
CE_F
and
RESET
are held at V
IH
, but not within VCC_F
±
0.3V, the device will be in the standby mode, but the standby
current will be greater. The device requires the standard
access time (t
CE
) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
CC3_F
in the DC Characteristics tables represent the standby
current specification.
相关PDF资料 |
PDF描述 |
|---|---|
| A82DL3244TG-70IF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3224 | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3224TG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3224TG-70UF | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3224UG-70U | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A82DL3234TG-70U | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3234TG-70UF | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3234UG-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3234UG-70F | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
| A82DL3234UG-70I | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL32x4T(U) 32 Megabit (4Mx8 Bit/2Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash |
发布紧急采购，3分钟左右您将得到回复。