参数资料
型号: A8513KLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 3/25页
文件大小: 0K
描述: IC LED DRVR AUTO BCKLGHT 16TSSOP
特色产品: Allegro A8513 LED Driver
标准包装: 1
拓扑: PWM,SEPIC,升压(升压)
输出数: 1
内部驱动器:
类型 - 主要: 车载,背光
类型 - 次要: 白色 LED
频率: 1.8MHz ~ 2.2MHz
电源电压: 4.5 V ~ 40 V
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 16-TSSOP-EP
包装: 标准包装
工作温度: -40°C ~ 125°C
其它名称: 620-1440-6
A8513
NC 1
NC 2
Wide Input Voltage Range, High Efficiency
Fault Tolerant LED Driver
Pin-out Diagram
16 NC
15 COMP
SW 3
14 GND
SW 1
10 COMP
OVP 4
VIN 5
FAULT 6
VDD 7
PAD
13 GND
12 ISET
11 EN/PWM
10 LED
OVP 2
VIN 3
FAULT 4
VDD 5
PAD
9 GND
8 ISET
7 EN/PWM
6 LED
NC 8
Terminal List Table
LP Package
9 NC
LY Package
Name
LP
Number
LY
Function
COMP
ˉFˉ ˉA ˉ ˉUˉˉLˉ ˉTˉ
GND
ISET
LED
NC
OVP
PAD
EN/PWM
SW
VDD
VIN
15
6
13,14
12
10
1,2,8,9,16
4
11
3
7
5
10
4
9
8
6
2
7
1
5
3
Output of the error amplifier and compensation node. Connect compensation network from
this pin to GND for control loop compensation.
This pin is used to indicate fault conditions. Logic low indicates that the A8513 has
a fault present.
Ground.
Connect the R ISET resistor between this pin and GND to set the 100% LED current level.
Connect the cathode of the LED string to this pin.
No connection.
This pin is used to sense an overvoltage condition. Connect a resistive divider from the
VOUT node to this pin to adjust the Overvoltage Protection (OVP).
Exposed pad of the package providing enhanced thermal dissipation. This pad must be
connected to the ground plane(s) of the PCB with at least 8 thermal vias, directly in the pad.
PWM dimming pin. Used to control LED intensity by using pulse width modulation.
The drain of the internal NMOS switch of the boost converter.
Output of internal LDO. Connect a 0.1 μ F decoupling capacitor between this pin and GND.
Input power to the A8513.
Thermal Characteristics* may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value
Unit
Package Thermal Resistance
(Junction to Ambient)
Package Thermal Resistance
(Junction to Pad)
R θ JA
R θ JP
LP package
LY package
On 4-layer PCB based on JEDEC standard
On 2-layer PCB with 3.8 in. 2 of copper area each side
On 4-layer PCB based on JEDEC standard
On 2-layer PCB with 2.5 in. 2 of copper area each side
34
43
48
48
2
oC/W
oC/W
oC/W
oC/W
oC/W
*To be verified by characterization. Additional thermal information available on the Allegro ? website.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
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