参数资料
型号: AC164142
厂商: Microchip Technology
文件页数: 20/38页
文件大小: 0K
描述: BOARD DAUGHTER PWR LINE MODEM
特色产品: AC164142 PICtail? Plus Daughter Board
标准包装: 1
系列: PICtail™ Plus
主要目的: 接口,电源线路收发器
嵌入式:
主要属性: AC 电源线收发器,BPSK 7.2 Kbps
次要属性: 需要 Explorer 16 板
已供物品: 2 板,线缆,文档
Consumer-band BPSK 7.2 kbps PLM PICtail? Plus Daughter Board User’s Guide
3.1.2
Configuration Files
Modem and application configuration has been split into several header files, each
responsible for a logically separated portion of the code. Each demonstration applica-
tion defines a config.h file that serves as a master configuration file and should
include, directly or indirectly, all other configuration files. The modem and framework
modules have their own main configuration files ( modem.h and framework.h ), normally
included by the master config.h file. These files can be found in the config
subdirectory of the relevant project directory.
The entire configuration of the low-level modem code has been placed into three
configuration files, which can be found in the modem configuration
subdirectory ...\modem\conf . These configuration files are:
? config_plm.h : Contains options common to all modulation algorithms imple-
mented and allows modulation scheme selection
? config_bpsk.h : Contains all BPSK configuration options
? config_fec.h : Contains the forward error correction configuration
All configuration options are extensively documented in the source code comments.
3.1.3
Configuration Settings
The following are the important configuration settings.
PLM_OE
This setting selects how the Output Enable (HiZ signal) for the transmit amplifier is
asserted. This option is hardware-dependent and must be left at its default value for the
daughter board provided in the kit. Possible options are:
? Drive low to enable, high impedance to disable (default)
? Drive low to enable, drive high to disable
? Drive high to enable, drive low to disable
PLM_OE_LAT
The LAT register bit of the Output Enable signal (assembler syntax). This setting must
be changed only if a non-default JP2 jumper configuration is used. This setting must
match the jumper setting on the daughter board.
PLM_OE_TRIS
The TRIS register bit of the Output Enable signal (assembler syntax). This must match
the setting for PLM_OE_LAT.
PLM_ADC_CHNL
This setting selects the ADC input number (i.e., ANx pin). The ADC configuration is
adjusted automatically. This setting must be changed only if a non-default JP3 jumper
configuration is used. This setting must match jumper setting on the daughter board.
PLM_ADC_TRIS
The TRIS register bit where the selected ANx channel is located.
PLM_FRAMING
This setting enables the low-level framing and is disabled by default.
PLM_SOF
The Start of Frame (SOF) character. This setting is used only if low-level framing is
enabled.
DS70656A-page 20
? 2011 Microchip Technology Inc.
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