参数资料
| 型号： | ACS8944T |
| 厂商： | Semtech |
| 文件页数： | 23/24页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 输入： | LVPECL |
| 输出： | LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 155.52MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 8
www.semtech.com
ACS8944 JAM PLL
VCP are the combined differential charge pump outputs
and VCO control voltage inputs. Figure 5 shows the
arrangement.
Figure 8 Loop Filter Components
All electrolytic capacitors should be low leakage and low
ESR (equivalent series resistance). Ceramic (preferred) or
tantalum are suitable for C1 and C3.
(phase margin 80.2°). Higher damping factors may be
used if lower transfer peaking is required. Contact
Semtech Sales Support for further details.
Output Jitter
The output jitter meets all requirements of ITU, Telcordia
and ETSI standards for SONET rates up to
OC-12/STM-4/622.08 MHz. See the “Electrical
Specifications” sections for details on the jitter figures
across the different output jitter frequency bands relevant
to each specification.
The recommended bandwidth of around 2 kHz is suitable
for both meeting the specification on output jitter
generation requirements and for filtering out the input
jitter from the input clock.
System Reset
After power-up or a system reset via the RESETB (pin 40),
the internal control logic waits for the presence of an input
signal of approximately the correct frequency (at least
40% of the nominal) and then allows a further settling
time of 60ms before allowing internal frequency tuning,
frequency-locking and phase-locking on to the input clock.
Consequently reset should be removed only when the
input frequency is within 400 ppm of the nominal
frequency.
Layout Recommendations
It is highly recommended to use a stable and filtered 3.3 V
power supply to the device. A separate filtered power and
ground plane is recommended with supply decoupling
capacitors of 10 nF and 100 pF utilizing good high
frequency chip capacitors (0402 or 0603 format surface-
mount package) on each VDD. Good differential signal
layout on the input and output lines should be used to
ensure matched track impedance and phase. Contact
Semtech directly for further layout recommendations.
Lock Detector
A simple lock detector is incorporated which combines the
plus and minus phase errors from the phase detector,
such that if any phase error signal is present, the LOCKB
output drives out a +10
A current, otherwise it is off.
Consequently this output (LOCKB) is a pulse width
modulated (PWM) pulse stream whose mark/space ratio
indicates the current input phase error. Filtering this
signal with a simple external RC parallel filter as shown in
Figure 9 will give a signal whose output level indicates PLL
phase and frequency lock.
Table 6 Loop Filter Components when using 19.44 MHz
or 77.76 MHz Input Frequency
Closed Loop
Bandwidth
R1 & R2
C2 & C4
C1 & C3
2 kHz
75
15
F
100 nF
4 kHz
150
4.7
F
33 nF
8 kHz
270
0.68
F7.5 nF
1.5 kHz
56
33
F
200 nF
Table 7 Loop Filter Components when using 38.88 MHz
or 155.52 MHz Input Frequency
Closed Loop
Bandwidth
R1 & R2
C2 & C4
C1 & C3
2 kHz
150
6.8
F
47 nF
4 kHz
300
2.2
F
22 nF
8 kHz
560
0.47
F3.9 nF
1.5 kHz(i)
110
15
F
91 nF
Note: (i) Not available at 155.52 MHz input frequency
VCP
VCN
JA
M
P
L
C1
R1
R2
C3
C4
GND
C2
F8944_010Loopfilter_01
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| ACS9010 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Optoelectronic |
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