参数资料
| 型号： | ACS8947T |
| 厂商： | Semtech |
| 文件页数： | 3/30页 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 标准包装： | 1 |
| 类型： | 时钟/频率发生器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太网，PCI，SONET/SDH，无线系统 |
| 输入： | LVPECL |
| 输出： | CML，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 625MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 托盘 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 11
www.semtech.com
Phase and Frequency Detector
The internal phase and frequency detector is designed to
operate across the full input frequency range of 580 kHz
to 180 MHz and includes the ALARMC_CO3 activity alarm.
Charge Pumps and External Low-Pass Filter
A differential charge pump is used to drive the external
loop filter via pins VCN and VCP. For linear operation of
the PLL, the differential voltage range is limited to ±1.2 V
centered around a typical common mode voltage of
1.25 V.
To maintain sensible external component values, the
magnitude of the charge pump current (IC) is dependent
on the OSC/8 divider ratio as defined in Table 6.
The closed loop PLL bandwidth is set by two identical sets
of passive RC components that connect to the differential
charge pump outputs pins VCN and VCP. Figure 5 shows
the recommended configuration of the second order loop
differential filter.
Figure 5 Configuration of Second Order Loop Filter
Refer to PLL Configuration for details on how to calculate
the loop filter component values for a given closed loop
bandwidth and phase margin. Automatic calculation is
available in the the ACS8947T evaluation software GUI.
Voltage Controlled Oscillator
The internal VCO operates across a frequency range of
2.35 GHz to 2.9 GHz. The VCO frequency is divided down
to the selected output rate, giving a precise 50/50
balanced mark/space ratio for the output.
Output Multiplexer and Divider
A 5-bit tapped, differential CML divider tree is used in
conjunction with the odd divider to generate the required
output frequencies. The divider ratios are set according to
the frequency list defined by the external configuration
wiring and cannot be modified once the device is locked.
The device automatically allocates the frequency list to
outputs as part of the PLL configuration sequence.
Outputs
Four programmable LVPECL/CML differential outputs are
provided via signal pairs OUT[4:1]N/P (pins 11/12, 8/9,
5/6 and 2/3). Interfacing to LVDS is also possible using
suitable passive components (see Input and Output
Interface Terminations). The frequency assigned to each
output is programable between 1.23 MHz and 625 MHz
and, during device reset, is set by the frequency map
defined by the configuration sequence. Although the
theoretical maximum output frequency of the PLL is
725 MHz, the output ports are only guaranteed to meet
VOH/VOL to a maximum of 625 MHz.
Each differential output has a dedicated power supply pin
that should be connected to VDD if the output is required
to be active. If an output port is not required, connect the
dedicated power pin to ground to disable the differential
output.
Table 6 Relationship of IC and OSC/8 Divider Ratio
IC (
μA)
OSC/8 Divide By
10
1 -> 2
40
3 -> 8
160
9 -> 24
210
25 -> 512
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相关代理商/技术参数 |
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| ACS9510EVB | 功能描述:EVALUATION BOARD FOR ACS9510 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:ToPSync™ 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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