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参数资料
| 型号： | ACT-7000ASC-300F17I |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 300 MHz, RISC PROCESSOR, CQFP208 |
| 封装： | 1.120 X 1.120 INCH, CERAMIC, QFP-208 |
| 文件页数： | 5/26页 |
| 文件大小： | 231K |
| 代理商： | ACT-7000ASC-300F17I |
13
SCD7000A Rev C 9/9/09
Aeroflex Plainview
Figure 7 shows a processor block read request and the
external agent read response for a system with a
transaction.
The read latency is 4 cycles (ValidOut* to ValidIn*),
and the response data pattern is DDxxDD. Figure 8 shows
a processor block write where the processor was
programmed with write-back data rate boot code 2, or
DDxxD-Dxx.
Data Prefetch
The ACT 7000ASC supports the MIPS IV integer data
prefetch (PREF) and floating-point data prefetch (PREFX)
instructions. These instructions are used by the compiler or
by an assembly language programmer when it is known or
suspected that an upcoming data reference is going to miss
in the cache. By appropriately placing a prefetch
instruction, the memory latency can be hidden under the
execution of other instructions. If the execution of a
prefetch instruction would cause a memory management or
address error exception the prefetch is treated as a NOP.
The “Hint” field of the data prefetch instruction is used
to specify the action taken by the instruction. The
instruction can operate normally (that is, fetching data as if
for a load operation) or it can allocate and fill a cache line
with zeroes on a primary data cache miss.
Enhanced Write Modes
The ACT 7000ASC implements two enhancements to
the original R4000 write mechanism: Write Reissue and
Pipeline Writes. In write reissue mode, a write rate of one
write every two bus cycles can be achieved. A write issues
if WrRdy* is asserted two cycles earlier and is still
asserted during the issue cycle. If it is not still asserted then
the last write will reissue. Pipe-lined writes have the same
two bus cycle write repeat rate, but can issue one additional
write following the deassertion of WrRdy*.
External Requests
The ACT 7000ASC can respond to certain requests
issued by an external device. These requests take one of
two forms: Write requests and Null requests. An external
device executes a write request when it wishes to update
one of the processors writable resources such as the internal
interrupt register. A null request is executed when the
external device wishes the processor to reassert ownership
of the processor external interface. Typically a null request
will be executed after an external device, that has acquired
control of the processor interface via ExtRqst*, has
completed an independent transaction between itself and
system memory in a system where memory is connected
directly to the SysAD bus. Normally this transaction would
be a DMA read or write from the I/O system.
Test / Breakpoint Registers
To increase both observability and controllability of the
processor
thereby
easing
hardware
and
software
debugging, a pair of Test/Break-point, or Watch, registers,
Watch1
and
Watch2,
have
been
added
to
the
ACT 7000ASC. Each Watch register can be separately
enabled to watch for a load address, a store address, or an
instruction address. All address comparisons are done on
physical addresses. An associated register, Watch Mask,
has also been added so that either or both of the Watch
registers can compare against an address range rather than
a specific address. The range granularity is limited to a
power of two.
When enabled, a match of either Watch register results
in an exception. If the Watch is enabled for a load or store
address then the exception is the Watch exception as
defined for the R4000 with Cause exception code
twenty-three. If the Watch is enabled for instruction
addresses then a newly defined Instruction Watch
exception is taken and the Cause code is sixteen. The
Watch register which caused the exception is indicated by
Cause bits 25..24.
Table 9 summarizes a Watch operation.
Table 9 – Watch Control Register
Register
Bit Field/Function
63
62
61
60:36
35:2
1:0
Watch1, 2 Store Load Instr
0
Addr
0
31:2
1
0
Watch
Mask
Watch
2
Mask
Watch
1
Data0
nData
Data1
nData
Addr
Read
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
SysClock
Data2 Data3
nData NEOD
Figure 7 – Processor Block Read
相关PDF资料 |
PDF描述 |
|---|---|
| ACT4445 | DATACOM, MIL-STD-1553 DATA BUS TRANSCEIVER, BCC64 |
| ACTS04KMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDFP14 |
| ACTS04DMSR-02 | ACT SERIES, HEX 1-INPUT INVERT GATE, CDIP14 |
| ACTS08DMSR | ACT SERIES, QUAD 2-INPUT AND GATE, CDIP14 |
| ACTS138HMSR-02 | ACT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, UUC16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ACT7000SC | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17C | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17I | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17M | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
| ACT-7000SC-150F17Q | 制造商:AEROFLEX 制造商全称:AEROFLEX 功能描述:ACT 7000SC 64-Bit Superscaler Microprocessor |
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