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参数资料
| 型号： | AD13280AF |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 68CLCC |
| 标准包装： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 80M |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 4.3W |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-CLCC |
| 供应商设备封装： | 68-CLCC（50.8x50.8） |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，双极 |
| 配用： | AD13280/PCB-ND - KIT EVAL PCB FOR AD13280 |
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AD13280
Rev. C | Page 17 of 28
EVALUATION BOARD
The AD13280 evaluation board (see Figure 20) is designed to
provide optimal performance for evaluation of the AD13280
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13280. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD13280. The digital outputs of the
AD13280 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
LAYOUT INFORMATION
The schematics of the evaluation board (Figure 21, Figure 22,
and Figure 23) represent a typical implementation of the
AD13280. The pinout of the AD13280 is very straightforward
and facilitates ease of use and the implementation of high
frequency/high resolution design practices. It is recommended
that high quality ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. All capacitors
can be standard, high quality ceramic chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
should connect directly to the receiving gate. Internal circuitry
buffers the outputs of the ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
02
38
6-
0
20
Figure 20. Evaluation Board Mechanical Layout
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD13280AZ | 功能描述:IC ADC 12BIT 68CLCC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| AD13280BF | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual-Channel, 12-Bit, 80 MSPS ADC with Analog Input Signal Conditioning |
| AD13280BZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning |
| AD132IV | 制造商:未知厂家 制造商全称:未知厂家 功能描述:TRANSISTOR | BJT | PNP | 60V V(BR)CEO | 3A I(C) | TO-3 |
| AD-132MC | 制造商:DATEL 功能描述: |
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