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参数资料
| 型号： | AD1555BPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC PGA 24BIT LN 28-PLCC |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 256k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 96mW |
| 电压电源： | 双 ± |
| 工作温度： | -55°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
REV. B
AD1555/AD1556
–11–
AD1556 PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Description
14
DOUT
Serial Data Output. DOUT is used to access the conversion results or the contents of the Status
Register, depending on the logic state of the RSEL pin. At the beginning of a read operation, the
first data bit is output (MSB first). The data changes on the rising edge of SCLK and is valid on the
SCLK falling edge.
15
DRDY
Data Ready. A logic high output indicates that data is ready to be accessed from the Output Data
Register. DRDY goes low once a read operation is complete. When selected, the DRDY output pin
has a type buffer that allows wired-OR connection of multiple AD1556s.
16
CS
Chip Select. When set low the serial data interface pins DIN, DOUT, R/
W, and SCLK are active; a
logic high disables these pins and sets the DOUT pin to Hi-Z.
17
R/
W
Read/Write. A read operation is initiated if R/
W is high and CS is low. A low sets the DOUT pin to
Hi-Z and allows a write operation to the device via the DIN pin.
18
RSEL
Register Select. When set high, the Conversion Data Register contents are output on a read opera-
tion. A low selects the Status Register.
19
DIN
Serial Data Input. Used during a write operation. Loads the Configuration Register via the Input
Shift Register. Data is loaded MSB first and must be valid on the falling edge of SCLK.
20
ERROR
Error Flag. A logic low output indicates an error condition occurred in the modulator or digital
filter. When
ERROR goes low the ERROR bit in the status register is set high. The ERROR output
pin has an open drain type buffer with an internal 100 k
typical pull-up that allows wired-OR
connection of multiple AD1556s.
25
RESET
Chip Reset. A logic high input clears any error condition in the status register and sets the configuration
register to the state of the corresponding hardware pins. On power-up, this reset state is entered.
26
PWRDN
Power-Down Hardware Control. A logic high input powers down the filter. The convolution cycles
in the digital filter and the MCLK signal are stopped. All registers retain their data and the serial
data interface remains active. The power-down mode is entered on the first falling edge of CLKIN
after PWRDN is taken high. When exiting the power-down mode, a SYNC must be applied to
resume filter convolutions.
29
CSEL
Filter Input Select. Selects the source for input to the digital filter. A logic high selects the TDATA
input, a low selects MDATA as the filter input.
30
TDATA
Test Data. Input to digital filter for user test data.
31
SYNC
Synchronization Input. The SYNC input clears the AD1556 filter in order to synchronize the start
of the filter convolutions. The SYNC event is initiated on the first CLKIN rising edge after the
SYNC pin goes high. The SYNC input can also be applied synchronously to the AD1556 decima-
tion rate without resetting the convolution cycles.
32
CLKIN
Clock Input. The clock input signal, nominally 1.024 MHz, provides the necessary clock for the
AD1556. This clock frequency is divided by four to generate the MCLK signal for the AD1555.
35
MCLK
Modulator Clock. Provides the modulator sampling clock frequency. The modulator always samples
at one-fourth the CLKIN frequency.
36
MDATA
Modulator Data. This input receives the ones-density bit stream from the AD1555 for input to the
digital filter.
37
RESETD
Decimator Reset. A logic high resets the decimator of the digital filter.
38
MFLG
Modulator Error. The MFLG input is used to detect if an overrange condition occurred in the
modulator. Its logic level is sensed on the rising edge of CLKIN. When overrange condition
detected, ERROR goes low and updates the status register.
43–39
CB0–CB4
Modulator Control. These output control pins represent a portion of the data loaded into the AD1556
Configuration Register. CB0–CB2 are generally used to set the PGA gain or cause it to enter in the
PGA standby mode (Refer to Table III). CB3 and CB4 select the mux input voltage applied to the
PGA as described in Table III.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1555BPZRL | 功能描述:IC ADC PGA 24BIT LN 28-PLCC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
| AD1556 | 制造商:AD 制造商全称:Analog Devices 功能描述:24-Bit ADC WITH LOW NOISE PGA |
| AD1556AS | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1556ASRL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP T/R |
| AD1556ASZ | 功能描述:IC ADC PGA 24BIT LN 44MQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
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