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参数资料
| 型号： | AD1833ACSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC AUDIO 24BIT 6CH 48LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1 |
| 位数： | 24 |
| 数据接口： | DSP，I²S，串行 |
| 转换器数目： | 6 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 12 电压，单极 |
| 采样率（每秒）： | 96k |
REV. 0
AD1833A
–11–
DAC Word Width
The AD1833A will accept input data in three separate word-
lengths—16 bits, 20 bits, and 24 bits. The word length may be
selected by writing to Control Bits 4 and 3 in DAC Control
Register 1 (see Table V).
Table V. Word Length Settings
Bit 4
Bit 3
Word Length
00
24 Bits
01
20 Bits
10
16 Bits
11
Reserved
Power-Down Control
The AD1833A can be powered down by writing to Control Bit 2
in DAC Control Register 1 (see Table VI).
Table VI. Power-Down Control
Bit 2
Power-Down Setting
0Normal Operation
1
Power-Down Mode
Interpolator Mode
The AD1833A’s DAC interpolators can be operated in one of
three modes—8 , 4
, or 2 — then correspond to 48 kHz, 96 kHz,
and 192 kHz modes, respectively (for IMCLK = 24.576 MHz). The
interpolator mode may be selected by writing to Control Bits 1
and 0 in DAC Control Register 1 (see Table VII).
Table VII. Interpolator Mode Settings
Bit 1
Bit 0
Interpolator Mode
00
8x (48 kHz)
*
01
2x (192 kHz)
*
10
4x (96 kHz)
*
11
Reserved
*For IMCLK = 24.576 MHz.
DAC CONTROL REGISTER 1
De-emphasis
The AD1833A has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
Redbook 50
ms/15 ms emphasis response curve. Three curves are
available, one each for 32 kHz, 44.1 kHz, and 48 kHz sampling
rates. The filters may be selected by writing to Control Bits 9
and 8 in DAC Control Register 1 (see Table III).
Table III. De-emphasis Settings
Bit 9
Bit 8
De-emphasis
00
Disabled
01
44.1 kHz
10
32 kHz
11
48 kHz
Data Serial Interface Mode
The AD1833A’s serial data interface is designed to accept data
in a wide range of popular formats including I
2S, right-justified
(RJ), left-justified (LJ), and flexible DSP modes. The L/RCLK
pin acts as the word clock (or frame sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1–SDIN3 pins. The serial
mode settings may be selected by writing to Control Bits 7
through 5 in the DAC Control Register 1 (see Table IV).
Table IV. Data Serial Interface Mode Settings
Bit 7
Bit 6
Bit 5
Serial Mode
0
00I
2S
0
01Right Justify
0
10
DSP
0
11Left Justify
1
00Packed Mode 1 (256)
1
01Packed Mode 2 (128)
1
10
TDM Mode
1
11Reserved
Table II. DAC Control Register 1
Function
Data-Word
Power-Down
Interpolator
Address
Reserved
1
De-emphasis
Serial Mode
Width
RESET
Mode
15–12
11
10
9–8
7–5
4–3
2
1–0
0000
0
00 = None
000 = I
2S
00 = 24 Bits
0 = Normal
00 = 8
(48 kHz)
2
01 = 44.1 kHz
001 = RJ
01 = 20 Bits
1 = PWRDWN
01 = 2
(192 kHz)
2
10 = 32.0 kHz
010 = DSP
10 = 16 Bits
10 = 4
(96 kHz)
2
11 = 48.0 kHz
011 = LJ
11 = Reserved
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = TDM Mode
111 = Reserved
NOTES
1Must be programmed to zero.
2For IMCLK = 24.576 MHz.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1833AST | 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC - Tape and Reel |
| AD1833AST-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1833CST | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1833CST-REEL | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1835 | 制造商:AD 制造商全称:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
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