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参数资料
| 型号： | AD1833ACSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC AUDIO 24BIT 6CH 48LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1 |
| 位数： | 24 |
| 数据接口： | DSP，I²S，串行 |
| 转换器数目： | 6 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 12 电压，单极 |
| 采样率（每秒）： | 96k |
REV. 0
AD1833A
–16–
Packed Mode 128
In Packed Mode 128, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 128
fS;
therefore, there are 128 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots: six slots of
20 BCLK and two of 4 BCLK. In this mode, the data length is
restricted to a maximum of 20 bits. The three left channels are
written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLK, and then the three right channels are writ-
ten. The L/
RCLK defines the left and right data transmission; it
is high for the three left channels and low for the three right channels.
Packed Mode 256
In Packed Mode 256, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 256
fS;
therefore, there are 256 BCLK periods in each sample interval, and
each sample interval is broken into eight time slots of 32 BCLK
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on the
falling edge of BCLK with a one BCLK period delay from the
start of the slot. After the three left channels are written, there is
a space of 32 BCLK, and then the three right channels are written.
The
L/RCLK defines the left and right data transmission; it is
low for the three left channels and high for the three right channels.
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
BLANK SLOT
4 SCLK
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BLANK SLOT
4 SCLK
DATA
20-BIT DATA
16-BIT DATA
BCLK
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
LSB
MSB
L/
RCLK
Figure 11. Packed Mode 128
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
20-BIT DATA
24-BIT DATA
16-BIT DATA
BCLK
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
LSB
+3
LSB
+2
LSB
+1
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
LSB
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
DATA
BCLK
L/RCLK
Figure 12. Packed Mode 256
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相关代理商/技术参数 |
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|---|---|
| AD1833AST | 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC - Tape and Reel |
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