参数资料
| 型号： | AD1893JSTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC SAMPLE-RATE CONV 16BIT 44TQFP |
| 标准包装： | 1 |
| 系列： | SamplePort™ |
| 类型： | 采样率转换器 |
| 应用： | 多媒体 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LQFP |
| 供应商设备封装： | 44-LQFP（10x10） |
| 包装： | 托盘 |
AD1893–SPECIFICATIONS
REV. A
–2–
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage
+3.0
V
Ambient Temperature
25
°C
Crystal Frequency
16
MHz
Load Capacitance
100
pF
All minimums and maximums tested except as noted.
PERFORMANCE
1 (Guaranteed for V
DD = +3.3 V to +5.0 V ± 10%)
Min
Max
Units
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
96
dB
Total Harmonic Distortion + Noise
(20 Hz to 20 kHz, Full-Scale Input, FSOUT/FSIN Between 0.51 and 1.99)
–94
dB
(1 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)
–96
dB
(10 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4)
–95
dB
Interchannel Phase Deviation
0
Degrees
Input and Output Sample Clock Jitter
(For
≤1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode)
10
ns
DIGITAL INPUTS
(Guaranteed for VDD = +3.0 V to +5.0 V ± 10%)
Min
Max
Units
VIH
2.0
V
VIL (VDD ≥ +3.0 V)
0.8
V
VIL (+2.7 V ≤ VDD < +3.0 V)
0.7
V
IIH @ VIH = +5.0 V, All Pins Except XTAL_I
4
A
IIH @ VIH = +5.0 V, XTAL_I Pin
6
A
IIL @ VIL = 0 V, All Pins Except XTAL_I
4
A
IIL @ VIL = 0 V, XTAL_I Pin
6
A
VOH @ IOH = –4 mA (VDD ≥ +3.0 V)
2.4
V
VOH @ IOH = –4 mA (+2.7 V ≤ VDD < +3.0 V)
2.2
V
VOL @ IOL = 4 mA
0.4
V
Input Capacitance
1
15
pF
DIGITAL TIMING
(Guaranteed for VDD = +3.0 V to +5.0 V ± 10%) See Figures 26 through 28.
Min
Max
Units
tCRYSTAL
Crystal Period
62.5
125
ns
FCRYSTAL
Crystal Frequency (1/tCRYSTAL)
16
MHz
tPWL
Crystal LO Pulsewidth
20
ns
tPWH
Crystal HI Pulsewidth
20
ns
FLRI
LR_I Frequency with 16 MHz Crystal
1
10
56
kHz
tRPWL
RESET LO Pulsewidth
125
ns
tRS
RESET Setup to Crystal Falling
15
ns
tBCLK
BCLK_I/O Period
1
120
ns
FBCLK
BCLK_I/O Frequency (l/tBCLK)
1
8.33
MHz
tBPWL
BCLK_I/O LO Pulsewidth
55
ns
tBPWH
BCLK_I/O HI Pulsewidth
55
ns
tWSI
WCLK_I Setup to BCLK_I
15
ns
tWSO
WCLK_O Setup to BCLK_O
40
ns
tLRSI
LR_I Setup to BCLK_I
15
ns
tLRSO
LR_O Setup to BCLK_O
55
ns
tDS
Data Setup to BCLK_I
0
ns
tDH
Data Hold from BCLK_I
35
ns
tDPD
Data Propagation Delay from BCLK_O
90
ns
tDOH
Data Output Hold from BCLK_O
15
ns
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