- 您现在的位置：买卖IC网 > PDF目录10218 > AD1941YSTZRL (Analog Devices Inc)IC DSP AUDIO 16CHAN 28BIT 48LQFP PDF资料下载
参数资料
| 型号： | AD1941YSTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/36页 |
| 文件大小： | 0K |
| 描述： | IC DSP AUDIO 16CHAN 28BIT 48LQFP |
| 标准包装： | 2,000 |
| 系列： | SigmaDSP® |
| 类型： | 音频处理器 |
| 应用： | 车载系统，家庭影院，电视 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
AD1940/AD1941
Rev. B | Page 16 of
36
of the byte sets either a read or write operation; Logic Level 1
corresponds to a read operation and Logic Level 0 corresponds
to a write operation. The seventh bit of the address is set by
tying the ADR_SEL pin of the AD1941 to Logic Level 0 or Logic
Level 1.
The AD1941 I2C port uses a spike filter that can be enabled or
disabled by the I2C_FILT_ENB pin. Enabling this filter guar-
antees that all isolated spikes, both positive and negative, less
than 50 ns wide are removed from the I2C signal. The filter is
active when the I2C_FILT_ENB pin is low and is disabled when
the pin is high. Typically, the largest spike that is filtered is
67 ns wide.
Table 12. AD1941 I2C Addresses
ADR_SEL
R/W
Slave Address
0
0x28
0
1
0x29
1
0
0x2A
1
0x2B
Addressing
Initially, all devices on the I2C bus are in an idle state, which is
where the devices monitor the SDA and SCL lines for a start
condition and the proper address. The I2C master initiates a
data transfer by establishing a start condition, defined by a
high-to-low transition on SDA while SCL remains high. This
indicates that an address/data stream will follow. All devices on
the bus respond to the start condition and read the next byte
(7-bit address + R/W bit) MSB first. The device that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition. The R/W bit
determines the direction of the data. A Logic 0 on the LSB of
the first byte means the master writes information to the
peripheral. A Logic 1 on the LSB of the first byte means the
master reads information from the peripheral. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically if a stop condition is not
encountered after a single-word write. The registers and
memories in the AD1941 range in width from one to five bytes,
so the autoincrement feature knows the mapping between sub-
addresses and the word length of the destination register (or
memory location). A data transfer is always terminated by a
stop condition.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
AD1941 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while in
autoincrement mode, one of two actions are taken. In read
mode, the AD1941 outputs the highest subaddress register
contents until the master device issues a no-acknowledge,
indicating the end of a read. A no-acknowledge condition is
where the SDA line is not pulled low on the ninth clock pulse
on SCL. If the highest subaddress location is reached while in
write mode, the data for the invalid byte is not loaded into any
subaddress register, a no-acknowledge is issued by the AD1941
and the part returns to the idle condition.
I2C Read and Write Operations
Table 13 shows the timing of a single-word write operation.
Every ninth clock, the AD1941 issues an acknowledge by
pulling SDA low.
Table 14 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The AD1941 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single word read operation is shown in Table
15. Note that the first R/W bit is still a 0, indicating a write
opera-tion. This is because the subaddress still needs to be
written in order to set up the internal address. After the
AD1941 acknow-ledges the receipt of the subaddress, the
master must issue a repeated start command followed by the
chip address byte with the R/W set to 1 (read). This causes the
AD1941’s SDA to turn around and begin driving data back to
the master. The master then responds every ninth pulse with an
acknowledge pulse to the AD1941.
Table 16 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The AD1941 knows to increment its subaddress register
every two bytes because the requested subaddress corresponds
to a register or memory area with word lengths of two bytes.
Other address ranges may have a variety of word lengths
ranging from one to five bytes; the AD1941 always decodes the
subaddress and sets the autoincrement circuit so that the
address increments after the appropriate number of bytes.
相关PDF资料 |
PDF描述 |
|---|---|
| AD1940YSTZRL | IC DSP AUDIO 16CH/28BIT 48-LQFP |
| SP3243EUEA-L/TR | IC TXRX RS232 INTELLIGENT 28SSOP |
| VE-21J-IU-F2 | CONVERTER MOD DC/DC 36V 200W |
| ADAU1446YSTZ-3A-RL | IC SIGMADSP 175MHZ 100LQFP |
| SP3243EUCA-L/TR | IC TXRX RS232 INTELLIGENT 28SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1953 | 制造商:AD 制造商全称:Analog Devices 功能描述:SigmaDSP⑩ 3-Channel, 26-Bit Signal Processing DAC |
| AD1953YST | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:3 CHANNEL 24 BIT SIGNAL-PROCESSING DAC - Tape and Reel 制造商:Analog Devices 功能描述:IC 24BIT DAC SMD 1953 LQFP48 |
| AD1953YSTRL | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP T/R |
| AD1953YSTRL7 | 制造商:Analog Devices 功能描述:DAC 3-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:3 CHANNEL 24 BIT SIGNAL-PROCESSING DAC - Tape and Reel |
| AD1953YSTZ | 功能描述:IC DSP DAC AUDIO3CH/26BIT 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:SigmaDSP® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
发布紧急采购，3分钟左右您将得到回复。