- 您现在的位置：买卖IC网 > PDF目录10965 > AD1970JSTZRL (Analog Devices Inc)IC ENCODER BTSC W/CODEC 48-LQFP PDF资料下载
参数资料
| 型号： | AD1970JSTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER BTSC W/CODEC 48-LQFP |
| 产品变化通告： | AD1970 Discontinuation 04/Apr/2012 |
| 标准包装： | 2,000 |
| 类型： | 音频编码器 |
| 应用： | 机顶盒，视频播放器，录音机 |
| 电压 - 电源，模拟： | 3 V ~ 3.6 V |
| 电压 - 电源，数字： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
AD1970
Rev. 0 | Page 16 of 20
ANALOG INPUT/OUTPUT
ADC INPUT
The AD1970 accepts an analog left-right signal on its input.
DAC OUTPUT
Figure 6 shows the block diagram of the analog output. A series
of current sources are controlled by a digital Σ-Δ modulator.
Depending on the digital code from the modulator, each cur-
rent source is connected to the summing junction of either a
positive I-to-V converter or a negative I-to-V converter. Two
extra current sources that push instead of pull are added to set
the midscale common-mode voltage.
All current sources are derived from the VREF input pin. The
gain of the AD1970 is directly proportional to the magnitude of
the current sources, and therefore the gain of the AD1970 is
proportional to the voltage generated on the VREF pin. The
nominal VREF voltage is 1.5 V.
IREF
IREF – DIG_IN
IREF + DIG_IN
SWITCHED CURRENT
SOURCES
VREF IN
OUT–
OUT+
FROM DIGITAL
Σ– MODULATOR
(DIG_IN)
05500-005
BIAS
Figure 6. Internal DAC Analog Architecture
Since the VREF input effectively multiplies the signal, care must
be taken to insure that no ac signals appear on this pin. This can
be accomplished by using a large decoupling capacitor con-
nected to VREF.
The AD1970 should be used with an external third order filter
on each output channel, as shown in Figure 8. The values shown
are for a 100 kHz Bessel filter. The use of a Bessel filter is impor-
tant to maintain the time-alignment of the pilot to the carrier. If
these signals are not in phase, a loss of separation occurs.
For best performance, a large (>10 F) capacitor should be
connected between the FILTCAP pin and analog ground.
SERIAL DATA PORT
The AD1970’s flexible serial audio interface accepts and sends
data in twos complement, MSB first format. The left channel
data field always precedes the right channel data field. The serial
mode is set by using mode select bits in the control register. In
all modes except for the right justified mode, the serial port
accepts an arbitrary number of bits up to a limit of 24 (extra bits
do not cause an error, but they are truncated internally). In the
right-justified mode, control register bits are used to set the
word length to 16, 20, or 24 bits. The default on power-up is 24-
bit mode. Proper operation of the right justified mode requires
that there be exactly 64 BCLKs per audio frame.
SERIAL DATA MODES
Figure 7 shows the left-justified mode. LRCLK is high for the
left channel, and low for the right channel. Data is sampled on
the rising edge of BCLK. The MSB is left-justified to a LRCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Figure 7 shows the I2S mode, which is the default setting.
LRCLK is low for the left channel and the MSB is delayed from
the edge of the LRCLK by a single BCLK period. The I2S mode
can be used to accept any number of bits up to 24.
Figure 7 shows the right-justified mode of the AD1970. LRCLK
is high for the left channel, low for the right channel. Data is
sampled on the rising edge of BCLK. The start of data is delayed
from the LRCLK edge by 16, 12, or 8 BCLK intervals, depending
on the selected word length. The default word length is 24 bits;
other word lengths are set by writing to Bits 1:0 of the control
register. In right-justified mode, it is assumed that there are 64
BCLKs per frame.
Figure 7 shows the DSP serial port mode. LRCLK must pulse
high for at least one bit clock period before the MSB of the left
channel is valid and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
valid. Data is sampled on the falling edge of BCLK. The DSP
serial port mode can be used with any word length up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse and that
synchronism is maintained from that point forward.
相关PDF资料 |
PDF描述 |
|---|---|
| ADV7177KSZ | IC DAC VIDEO NTSC 3-CH 44MQFP |
| VI-24L-CU-S | CONVERTER MOD DC/DC 28V 200W |
| VI-24K-CU-S | CONVERTER MOD DC/DC 40V 200W |
| VI-24J-CU-S | CONVERTER MOD DC/DC 36V 200W |
| VI-241-CU-S | CONVERTER MOD DC/DC 12V 200W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1974 | 制造商:AD 制造商全称:Analog Devices 功能描述:4 ADC with PLL, 192 kHz, 24-Bit Codec |
| AD1974WBSTZ | 制造商:Analog Devices 功能描述: |
| AD1974WBSTZ-RL | 功能描述:ADC, Audio 24 bit 192k I2S 48-LQFP (7x7) 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 类型:ADC，音频 分辨率（位）:24 b 采样率（每秒）:192k 数据接口:I2S 电压源:模拟和数字 电压 - 电源:3 V ~ 3.6 V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商器件封装:48-LQFP（7x7） 标准包装:2,000 |
| AD1974YSTZ | 功能描述:IC ADC 4CH W/ON-CHIP PLL 48LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD1974YSTZ-RL | 功能描述:IC CODEC 4CH ADC W/PLL 48-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
发布紧急采购，3分钟左右您将得到回复。